Skip to main content
SpringerLink
Log in

A power-efficient 2-dimensional on-chip eye-opening monitor for Gbps serial links

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper investigates the drawbacks of widely used rectangular eye-opening monitors (EOMs) and proposes a new power-efficient half hexagon EOM for Gbps serial links. The proposed EOM outperforms rectangular EOMs by providing a better control of data jitter at the edge of data eyes and by eliminating unnecessary errors flagged by rectangular EOMs. The effectiveness of the proposed EOM is evaluated using a serial link implemented in IBM 130 nm 1.2 V CMOS technology. For purpose of comparison, rectangular EOMs with the same data link are also designed and evaluated. The data links are analyzed using Spectre from Cadence Design Systems with BSIM 4 device models. Simulation results demonstrate that the proposed EOM provides a better detection of the violation of the minimum eye-opening mask over temperature range −20 to 80 °C and at all process corners as compared with rectangular EOM, with 50 % reduction in power and silicon consumption.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20

Similar content being viewed by others

References

  1. Zhao, Z., Wang, J., Li, S., Chen, J. (2007). A 2.5-Gb/s 0.13 μm CMOS current mode logic transceiver with pre-emphasis and equalization. Proceedings of International Conference ASIC, (pp.368–371) Oct 2007.

  2. Kao, S., Liu, S. (2010). A 20-Gb/s transmitter with adaptive pre-emphasis in 65-nm CMOS technology. IEEE Transaction of Circuits and Systems II, 57(5), 319–323.

    Article  Google Scholar 

  3. Dally, J., Poulton, J. (1997). Transmitter equalization for 4-gbps signaling. IEEE Micro, 17(1), 48–56.

    Article  Google Scholar 

  4. Ying, Y., Liu, S. (2011, Feb). A 20Gb/s digitally adaptive equalizer/DFE with blind sampling. IEEE International Solid-State Circuits Conference Digital Technology Papers (pp.444–446) 2011.

  5. Dickson, T., Bulzacchelli, J., Friedman, D. (2009). A 12Gb/s 11 mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology. IEEE Journal of Solid-State Circuits, 44(4), 1298–1230.

    Article  Google Scholar 

  6. Bien, F., Kim, H., Hur, Y., Maeng, M., Cha, J., Chandramouli, S., Gebara, E., Laskar, J. (2006). A 10 Gb/s reconfigurable CMOS equalizer employing a transition detector-based output monitoring technique for band-limited serial links. IEEE Transactions on Microwave Theory and Techniques, 54(12), 4538–4547.

    Article  Google Scholar 

  7. Hyoungsoo, K., de Ginestous, J., Bien, F., Lee, K., Chandramouli, S., Hur, Y., Scholz, C., Gebara, E., Laskar, J. (2007). An electronic dispersion compensator (EDC) with an analog eye-opening monitor (EOM) for 1.25 Gb/s gigabit passive optical network (GPON) upstream links. IEEE Transactions on Microwave Theory and Techniques, 55(12), 2942–2950.

    Article  Google Scholar 

  8. Hong, D., Cheng, K. (2007). An accurate jitter estimation technique for efficient high speed I/O testing. Proceedings of the Asian Test Symposium, (pp.224–229) Oct 2007.

  9. Chen, L., Zhang, X., Spagna, F. (2009, Feb). A scalable 3.6-5.2 mW 5-to-10 Gb/s 4-tab DFE in 32 nm. IEEE International Solid-State Circuits Conference Digital Technology Papers, (pp.180–181).

  10. Spagna, F., Chen, L., Deshpande, M., Fan, Y., Gambetta, D., Gowder, S., Iyer, S., Kumar, R., Kwok, P., Krishnamurthy, R., Lin, C., Mohanavelu, R., Nicholson, R., Ou, J., Pasquarella, M., Prasad, K., Rustam, H., Tong, L., Tran, A., Wu, J., Zhang, X. (2010, Feb). A 78 mw 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32 nm CMOS. IEEE International Solid-State Circuits Conference Digital Technology Papers, (pp. 366–367).

  11. Pozzoni, M., Erba, S., Viola, P., Pisati, M., Depaoli, E., Sanzogni, D., Brama, R., Baldi, D., Repossi, M., Svelto, F. (2009). A multi-standard 1.5 to 10 Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication. IEEE Journal of Solid-State Circuits, 44(4), 1306–1315.

    Article  Google Scholar 

  12. Analui, B., Rylyakov, A., Rylov, S., Meghelli, M., Hajimiri, A. (2005). A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS. IEEE Journal of Solid-State Circuits, 40(12), 2689–2699.

    Article  Google Scholar 

  13. Noguchi, H., Yoshida, N., Uchida, H., Ozaki, M., Kanemitsu, S., Wada, S. (2008). A 40-Gb/s CDR circuit with adaptive decision-point control based on eye-opening monitor feedback. IEEE Journal of Solid-State Circuits, 43(12), 2929–2938.

    Article  Google Scholar 

  14. Bhatta, D., Kim, K., Gebara, E., Laskar, J. (June 2009). A 10 Gb/s two dimensional scanning eye opening monitor in 0.18μm CMOS process. Proceedings on IEEE International Microwave Symposium Digest (pp.1141–1144).

  15. Fayed, A., Ismail, M. (2008). A low-voltage low-power CMOS analog adaptive equalizer for UTP-5 cables. IEEE Transactions on Circuits and Systems I., 55(2), 480–495.

    Article  MathSciNet  Google Scholar 

  16. Marcu, M., Durbha, S., Gupta, S. (2008). Duty-cycle distortion and specifications for jitter test-signal generation. Proceedings on IEEE International Symposium Electromagnetic Compatibility (pp.1–4).

  17. Carusone, T., Johns, D., Martin, K. (2008). Analog integrated circuit design. New York: Wiley

    Google Scholar 

Download references

Acknowledgments

This Project was financially supported by Natural Sciences and Engineering Research Council of Canada and in part by computer-aided design tools from CMC Microsystems, Kingston, ON, Canada.

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Ryerson University, M5B 2K3, Toronto, ON, Canada

    Alaa R. AL-Taee, Fei Yuan & Andy Ye

Authors
  1. Alaa R. AL-Taee
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Fei Yuan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Andy Ye
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Fei Yuan.

Rights and permissions

Reprints and permissions

About this article

Cite this article

AL-Taee, A.R., Yuan, F. & Ye, A. A power-efficient 2-dimensional on-chip eye-opening monitor for Gbps serial links. Analog Integr Circ Sig Process 76, 117–128 (2013). https://doi.org/10.1007/s10470-013-0083-1

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-013-0083-1

Keywords

Search

Navigation