Skip to main content
SpringerLink
Log in

An edge-based dual adaptive decision feedback equalizer for Gbps serial links

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents an adaptive edge-DFE for 2PAM Gbps serial links. The optimal tap coefficients of the DFE are obtained by minimizing the jitter of received data. Reference voltage for generating DFE error signal is also obtained iteratively using an edge-DFE like algorithm. Issues critical to the proposed adaptive edge-DFE are examined in detail. The effectiveness of the proposed adaptive edge-DFE has been validated using a 5 Gbps serial link designed in a 65 nm 1.2 V CMOS technology. The effect of PVT (process, voltage, and temperature) variations on the performance of the proposed DFE has also been investigated. Simulation results demonstrate that the DFE is capable of opening completely closed data eyes when the DFE is absent. Equalized data have 55 % vertical-opening and 86.5 % horizontal eye-opening with 25 ns adaption time.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

Notes

  1. Pravin Patel and Barry Barnett, “Experimental Test Fixture S-parameters 100 Gb/s Backplane Study Group,” IBM Corporation. http://www.ieee802.org/3/100GCU/public/channel.html.

References

  1. Austin, M. (1967). Decision-feedback equalization for digital communication over dispersive channels. IEEE Int’l Research Laboratory of Electronics Technical Report, 461.

  2. Yuan, F., Al-Taee, A., Ye, A., & Sadr, S. (2013). Design techniques for decision feedback equalization of multi-Gbp1s serial data links: A state-of-the-art review. IET Circuits Devices and Systems, 8, 118–130.

    Article  Google Scholar 

  3. Cui, H., Lee, J., Jeon, S., Bae, S., Sohn, Y., Sim, J., et al. (2011). A single-loop SS-LMS algorithm with single-ended integrating DFE receiver for multi-drop DRAM interface. IEEE Journal of Solid-State Circuits, 46(9), 2053–2063.

    Article  Google Scholar 

  4. Krishna, K., Yokoyama-Martin, D., Caffee, A., Jones, C., Loikkanen, M., Parker, J., et al. (2005). A multi-giga-bit backplane transceiver core in 0.13-\(\mu\)m CMOS with a power-efficient equalization architecture. IEEE Journal of Solid-State Circuits, 40(12), 2658–2666.

    Article  Google Scholar 

  5. Shahramian, S., Yasotharan, H., & Carusone, A. (2012). Decision feedback equalizer architectures with multiple continuous-time infinite impulse response filters. IEEE Transactions on Circuits System II, 59(6), 226–230.

    Article  Google Scholar 

  6. Bien, F., Kim, H., Hur, Y., Maeng, M., Cha, J., Chandramouli, S., et al. (2006). A 10 Gb/s reconfigurable CMOS equalizer employing a transition detector-based output monitoring technique for band-limited serial links. IEEE Transactions Microwave Theory Techniques, 54(12), 4538–4547.

    Article  Google Scholar 

  7. Hong, D. & Cheng, K. (2007). An accurate jitter estimation technique for efficient high speed I/O testing. In Proceedings of Asian Test Symposium (pp. 224 –229).

  8. Hong, D., Chen, L., Zhang, X., & Spagna, F. (2009). A scalable 3.6-5.2 mW 5-to-10 Gb/s 4-tab DFE in 32 nm. In IEEE Int’l Solid-State Circuits Conference Digesi Technical Papers (pp. 180–181).

  9. Spagna, F., Chen, L., Deshpande, M., Fan, Y., Gambetta, D., Gowder, S., Iyer, S., Kumar, R., Kwok, P., Krishnamurthy, R., Lin, C., Mohanavelu, R., Nicholson, R., Ou, J., Pasquarella, M., Prasad, K., Rustam, H., Tong, L., Tran, A., Wu, J., & Zhang X. (2010) A 78 mw 11.8 Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32 nm CMOS. IEEE Int’l Solid-State Circuits Conference Digest Technical Papers (pp. 366–367).

  10. Pozzoni, M., Erba, S., Viola, P., Pisati, M., Depaoli, E., Sanzogni, D., et al. (2009). A multi-standard 1.5 to 10 Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication. IEEE Journal of Solid-State Circuits, 44(4), 1306–1315.

    Article  Google Scholar 

  11. Noguchi, H., Yoshida, N., Uchida, H., Ozaki, M., Kanemitsu, S., & Wada, S. (2008). A 40-Gb/s CDR circuit with adaptive decision-point control based on eye-opening monitor feedback. IEEE Journal of Solid-State Circuits, 43(12), 2929–2938.

    Article  Google Scholar 

  12. Bhatta, D., Kim, K., Gebara, E., & Laskar, J. (2009) A 10 Gb/s two dimensional scanning eye opening monitor in 0.18\(\mu\)m CMOS process. In Proceedings of IEEE Int’l Microwave Symposium Digest (pp. 1141–1144).

  13. Al-Taee, A., Yuan, F., Ye, A., & Sadr, S. (2014). New 2d eye-opening monitor for gbps serial links. IEEE Transactions on Very Large Scale Integration Systems, 22(6), 1209–1218.

    Article  Google Scholar 

  14. Gerfers, F., Besten, G., Petkov, P., Conder, J., & Koellmann, A. (2008). A 0.2-2 Gb/s 6x OSR receiver using a digitally self-adaptive equalizer. IEEE Journal of Solid-State Circuits, 43(6), 1436–1448.

    Article  Google Scholar 

  15. Wong, K., Chen, E., & Yang, C. (2008). Edge and data adaptive equalization of serial-link transceivers. IEEE Journal of Solid-State Circuits, 43(9), 2157–2169.

    Article  Google Scholar 

Download references

Acknowledgments

Financial support from the Natural Science and Engineering Research Council of Canada and computer-aided design tools provided by CMC Microsystems, Kingston, ON, Canada are gratefully acknowledge.

Author information

Author notes

  1. Alaa R. AL-Taee

    Present address: Department of Electronics, Australian College of Kuwait, Kuwait City, Kuwait

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada

    Alaa R. AL-Taee, Matthew Dolan & Fei Yuan

Authors
  1. Alaa R. AL-Taee
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Matthew Dolan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Fei Yuan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Fei Yuan.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

AL-Taee, A.R., Dolan, M. & Yuan, F. An edge-based dual adaptive decision feedback equalizer for Gbps serial links. Analog Integr Circ Sig Process 90, 399–409 (2017). https://doi.org/10.1007/s10470-016-0804-3

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-016-0804-3

Keywords

Search

Navigation