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A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system

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Abstract

In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding–interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.

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Acknowledgments

This research was supported by the MSIP (Ministry of Science, ICT & Future Planning), Korea, under the C-ITRC (Convergence Information Technology Research Center) support program (NIPA-2013-H0301-13-1007) supervised by the NIPA (National IT Industry Promotion Agency), AIPRC.

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  1. Department of Semiconductor Science, Dongguk University-Seoul, 3-26, Phil-dong, Chung-ku, Seoul, Korea

    Seongjoo Lee & Minkyu Song

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  1. Seongjoo Lee
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  2. Minkyu Song
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Correspondence to Minkyu Song.

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Lee, S., Song, M. A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system. Analog Integr Circ Sig Process 76, 15–21 (2013). https://doi.org/10.1007/s10470-013-0080-4

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  • DOI: https://doi.org/10.1007/s10470-013-0080-4

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