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An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique

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Abstract

An 8-bit 2 GS/s 80 mW low power and high accurate CMOS folding A/D converter with a 45 nm CMOS process is described. In order to improve the non-linearity error of a conventional folding amplifier, a new symmetrical zero-crossing technique is proposed. Further, a digital error correction logic to rectify the distortion errors of analog blocks is also discussed. The proposed chip has been fabricated with 1.2 V 45 nm Samsung CMOS technology. The effective chip area is 1.98 mm2 and the power dissipation is about 80 mW. The measured result of SNDR is about 38 dB, when the input frequency is 1 GHz at the sampling frequency of 2 GS/s. The measured INL is within +2.5 LSB/−2.0 LSB and DNL is within +1.0 LSB/−1.0 LSB.

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Acknowledgments

This work was supported by a grant-in-aid of Hanwha Thales and Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2015R1D1A1A01058193).

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Authors and Affiliations

  1. Department of Semiconductor Science, Dongguk University, Seoul, Korea

    Daehyeok Kim, Sunghyun Park & Minkyu Song

  2. Hanwha Thales. Co. Ltd, Yongin, Korea

    Munkyo Lee

  3. Agency for Defense Development, Daejeon, Korea

    Sunphil Nah

Authors
  1. Daehyeok Kim
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  2. Sunghyun Park
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  3. Munkyo Lee
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  4. Sunphil Nah
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  5. Minkyu Song
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Correspondence to Minkyu Song.

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Kim, D., Park, S., Lee, M. et al. An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique. Analog Integr Circ Sig Process 86, 407–415 (2016). https://doi.org/10.1007/s10470-016-0693-5

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  • DOI: https://doi.org/10.1007/s10470-016-0693-5

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