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Single event crosstalk prediction in nanometer technologies

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Abstract

As CMOS technology continues to scale down, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. On the other hand, coupling effects among interconnects can cause single event transients to contaminate electronically unrelated circuit paths which may increase the SE susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event hardening, modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work, for the first time, proposes an SE crosstalk noise estimation method for use in design automation tools. The proposed method uses an accurate 4-π model for interconnect and correctly models the effect of non-switching aggressors as well as aggressor tree branches noting the resistive shielding effect. The SE crosstalk noise expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is about 5.2% while allowing for very fast analysis in comparison to HSPICE.

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References

  1. International technology roadmap for semiconductors. (2009 ed.). San Jose, CA: Semiconductor Industry Association (SIA) (2009).

  2. Mitra, S., Karnik, T., Seifert, N., & Zhang, M. (2005). Logic soft errors in sub-65 nm technologies design and CAD challenges. In Proceedings of DAC (pp. 2–3), June 2005.

  3. Dodd, P. E., & Massengill, L. W. (2003). Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Transactions on Nuclear Science, 50(3), 583–602.

    Article  Google Scholar 

  4. Balasubramanian, A., Sternberg, A. L., Bhuva, B. L., & Massengill, L. W. (2006). Crosstalk effects caused by single event hits in deep sub-micron CMOS technologies. IEEE Transactions on Nuclear Science, 53(6), 3306–3311.

    Article  Google Scholar 

  5. Balasubramanian, A., Amusan, O. A., Bhuva, B. L., Reed, R. A., Sternberg, A. L., Andrew, L., et al. (2008). Measurement and analysis of interconnect crosstalk due to single events in a 90 nm CMOS technology. IEEE Transactions on Nuclear Science, 55(4), 2079–2084.

    Article  Google Scholar 

  6. Sayil, S., Akkur, A. B., & Gaspard, N. (2009). Single event crosstalk shielding for CMOS logic. Microelectronics Journal, 40(6), 1000–1006.

    Article  Google Scholar 

  7. Normand, E. (1996). Single-event effects in avionics. IEEE Transactions on Nuclear Science, 43(2), 461–474.

    Article  Google Scholar 

  8. Bradley, P. D., & Normand, E. (2004). Single event upset in implantable cardioverter defibrillators. IEEE Transactions on Nuclear Science, 45(6), 2929–2940.

    Article  Google Scholar 

  9. Heydari, P., & Pedram, M. (2005). Capacitive coupling noise in high-speed VLSI circuits. IEEE Transactions on Computer Aided Design, 24(3), 478–488.

    Article  Google Scholar 

  10. Becer, M. R., Blaauw, D., Zolotov, V., Panda, & R., Hajj, I. N. (2002). Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model. In Proceedings of 2002 design, automation and test in Europe conference (pp. 456–464).

  11. Sayil, S., & Rudrapati, M. (2009). Accurate prediction of crosstalk for RC interconnects. Turkish Journal of Electrical Engineering, 17(1), 55–67.

    Google Scholar 

  12. Kawaguchi, H., & Sakurai, T. (1998). Delay and noise formulas for capacitively coupled distributed RC lines. In Proceedings of Asian South Pacific design automation conference (pp. 35–38).

  13. Rajappan, V., & Sapatnekar, S. (2003). An efficient algorithm for calculating the worstcase delay due to crosstalk. In Proceedings of ICCD (pp. 76–81).

  14. Irajpour, S., Nazarian, S., Wang, L., Gupta, S. K., & Breuer, M. A. (2003). Analyzing crosstalk in the presence of weak bridge defects. In Proceedings of VLSI Test symposium (VTS) (pp. 385–392).

  15. Zhou, Q., & Mohanram, K. (2006). Gate sizing to radiation harden combinational logic. IEEE Transactions on Computer-Aided Design, 25(1), 155–166.

    Article  Google Scholar 

  16. Hutson, J. M., Ramachandran, V., Bhuva, B. L., Zhu, X., Schrimpf, R. D., Amusan, O. A., et al. (2006). Single event induced error propagation through nominally-off transmission gates. IEEE Transactions on Nuclear Science, 53(6), 3558–3562.

    Article  Google Scholar 

  17. Freeman, L. B. (1996). Critical charge calculations for a bipolar SRAM array. IBM Journal of Research and Development, 40, 119–129.

    Article  Google Scholar 

  18. Ness, D. C., Hescott, C. J., & Lilja, D. J. (2007). Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations. In IEEE international symposium on nanoscale architectures (pp. 46–53).

  19. Levy, R., Blaauw, D., Braca, G., Dasgupta, A., Grinshpon, A., Oh, C., Orshav, B., Sirichotiyakul, S., & Zolotov, V. (2002). Clarinet: A noise analysis tool for deep submicron design. In Proceedings of international conference on C.A.D. (pp. 587–594), November 2002.

  20. Choudhury, M. R., Zhou, Q., & Mohanram, K. (2006). Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. In Proceedings of the 2006 IEEE/ACM international conference on C.A.D. (pp. 204–209).

  21. Qian, J., Pullela, S., & Pillage, L. T. (1994). Modeling the effective capacitance for the RC interconnect of CMOS gates. IEEE Transactions on Computer-Aided Design, 13, 1526–1535.

    Article  Google Scholar 

  22. Pillage, L. T., & Rohrer, R. A. (1990). Asymptotic waveform evaluation for timing analysis. IEEE Transactions on Computer-Aided Design, 9(4), 352–366.

    Article  Google Scholar 

  23. Acar, E., Odabasioglu, A., Celik, M., & Pileggi, L. (1999). S2p: A stable 2-pole RC delay and coupling noise metric IC interconnects. In Proceedings of 9th Great Lakes symposium on VLSI (pp 60–63).

  24. Predictive Technology Model (PTM). (2010). http://www.eas.asu.edu/~ptm.

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Acknowledgment

This work was supported in part by NASA Texas Space Grant Consortium (TSGC) Higher Education Grant.

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Authors and Affiliations

  1. Drayer Department of Electrical Engineering, Lamar University, P.O. 10029, Beaumont, TX, 77710, USA

    Selahattin Sayil & Vijay K. Boorla

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  1. Selahattin Sayil
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  2. Vijay K. Boorla
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Correspondence to Selahattin Sayil.

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Sayil, S., Boorla, V.K. Single event crosstalk prediction in nanometer technologies. Analog Integr Circ Sig Process 72, 205–214 (2012). https://doi.org/10.1007/s10470-011-9748-9

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  • DOI: https://doi.org/10.1007/s10470-011-9748-9

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