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Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

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Abstract

This low-power \(\Sigma\Delta\) modulator targets the DVB-H requirements and achieves about 10 bit with 6-MHz signal band. Suitable topological modifications enable the realization of a third order modulator with two op-amps. Moreover, a technique for swing reduction of the last op-amp strongly reduces the number of comparators in the quantizer. The power reduction techniques limit the consumption to 6.18 mW, thus yielding a FoM of 0.58 pJ/conversion. The area of the circuit, fabricated with a 0.18-μm analog CMOS technology, is 0.32 mm2. Experimental measurements confirm the behavioral study made accounting for the op-amps limitations.

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Acknowledgments

The authors would like to thank Ivano Galdi for valuable suggestions, National Semiconductor Corporation for chip fabrication, CONACyT Mexico project #J45732-Y, and FIRB, Italian National Program #RBAP06L4S5, for partial economical support.

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Authors and Affiliations

  1. Department of Electronics, University of Pavia, Via Ferrata, 1, 27100, Pavia, Italy

    Edoardo Bonizzoni, Aldo Peña Perez & Franco Maloberti

  2. Universidad Autonoma de Baja California, Mexicali, Baja California, Mexico

    Miguel A. Garcia-Andrade

Authors
  1. Edoardo Bonizzoni
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  2. Aldo Peña Perez
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  3. Franco Maloberti
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  4. Miguel A. Garcia-Andrade
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Correspondence to Edoardo Bonizzoni.

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Bonizzoni, E., Perez, A.P., Maloberti, F. et al. Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption. Analog Integr Circ Sig Process 66, 381–388 (2011). https://doi.org/10.1007/s10470-010-9538-9

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  • DOI: https://doi.org/10.1007/s10470-010-9538-9

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