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Multiband RF-sampling receiver front-end with on-chip testability in 0.13 μm CMOS

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Abstract

In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 2× subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.

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Acknowledgment

We are thankful to ACREO AB, Norrkoping, Sweden for providing us the access to there measurement lab and the assistance of Wasim Muhammad in the layout of LNA and RF test attenuator is also appreciated.

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Authors and Affiliations

  1. Department of Electrical Engineering, Linkoping University, Linkoping, SE 581 83, Sweden

    Rashad Ramzan, Stefan Andersson, Jerzy Dabrowski & Christer Svensson

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  1. Rashad Ramzan
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  2. Stefan Andersson
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  3. Jerzy Dabrowski
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  4. Christer Svensson
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Correspondence to Rashad Ramzan.

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Ramzan, R., Andersson, S., Dabrowski, J. et al. Multiband RF-sampling receiver front-end with on-chip testability in 0.13 μm CMOS. Analog Integr Circ Sig Process 61, 115–127 (2009). https://doi.org/10.1007/s10470-009-9286-x

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  • DOI: https://doi.org/10.1007/s10470-009-9286-x

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