1 Introduction

The development of complex structures for Systems on Chip (SoC) architecture is increasingly becoming dependent on compact mixed-signal systems, embedding high performance analog blocks with complex digital circuitry on the same chip. This necessitates the design of small and simple DACs. Unfortunately, to achieve an acceptable resolution and good performance, a considerable amount of complexity and silicon area is required. Power consumption is also a dominant factor in IC design [1].

The design of DACs based on standard CMOS technologies has been pursued to overcome these constraints with some success [2–7]. Although each of the converters have some attractive features, in the form of either consuming low power [2–5], or possessing good dynamic performance [6], all of them consist of segmented or matrix architecture, rendering a complexity to the D/A converter circuit.

In this paper, a novel topology to design DACs by exploiting the ability of Floating Gate MOSFET (FGMOS) [8], a device introduced in the last decade and used frequently in digital designs, to achieve a weighted sum of input voltages is presented. Though D/A conversion through FGMOS can also be obtained using different approaches such as programming of floating gate charge [9, 10], etc., the resultant DAC is relatively complicated. The proposed circuit shows good accuracy and dynamic performance and its simple architecture and low power consumption make it quite promising for integration.

2 FGMOS transistor

An n-input FGMOS transistor consists of a gate electrode which is left electrically floating. This floating gate is capacitively coupled to an array of n control gates through a second polysilicon layer. The terminal voltages and various capacitive coupling coefficients are defined in Fig. 1(b), where V FG is the floating gate potential, V 1, V 2...V n are the input signal voltages and C 1, C 2...C n are the capacitive coupling coefficients between the floating gate and each of the input gates.

Fig. 1
figure 1

FGMOST (a) Symbol (b) Equivalent circuit

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Let Q FG denote the net charge on the floating gate, which is calculated as

$$ Q_{{{{FG}}}} = {\sum\limits_{i = 1}^n {(V_{i} - V_{{{{FG}}}} )C_{i} } } + (V_{{{S}}} - V_{{{{FG}}}} )C_{{{S}}} + (V_{{{D}}} - V_{{{{FG}}}} )C_{{{D}}} + (V_{{{B}}} - V_{{{{FG}}}} )C_{{{B}}} $$
(1)

where C S , C D and C B are the parasitic capacitances between gate and source, drain and body, respectively. V S , V D and V B are the potentials at the respective terminals.

Under normal circumstances, Q FG is equal to the initial charge on the floating gate, which is assumed to be zero in this case for simplicity. Then Eq. 1 reduces to

$$ V_{{{{FG}}}} = \frac{{{\sum\limits_{i = 1}^n {C_{i} V_{i} } } + C_{{{S}}} V_{{{S}}} + C_{{{D}}} V_{{{D}}} + C_{{{B}}} V_{{{B}}} }} {{{\sum\limits_{i = 1}^n {C_{i} } } + C_{{{S}}} + C_{{{D}}} + C_{{{B}}} }} $$
(2)

Since C S , C D and C B are quite small in comparison to the capacitive coefficients, C i , Eq. 2 can be safely approximated to

$$ V_{{{{FG}}}} \approx {\sum\limits_{i = 1}^n {k_{i} V_{i} } } $$
(3)

where k i  = C i /C Total and

$$ C_{{{{Total}}}} \approx {\sum\limits_{i = 1}^n {C_{i} } } $$
(4)

3 Principle of operation and design

The proposed approach for the design of the n-input DAC is explained through the circuit structure shown in Fig. 2. Transistors M1 and M2 are multiple input floating gate MOSFETs (MIFG) with n and two gate inputs, respectively.

Fig. 2
figure 2

Proposed n-bit DAC

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Now V FG1, the floating gate potential of M1, can be written as

$$ V_{{{{FG}}1}} \approx {\sum\limits_{i = 1}^n {k_{i} V_{i} + k_{{{{T}}1}} {\left( {\frac{{V_{{{T}}} }} {{k_{{{{T}}1}} }}} \right)}} } $$
(5)

where k T1 = C T1/C Total1, C T1 and C Total1 being the capacitive coupling coefficient of the topmost control gate of M1 and total capacitance of M1, respectively, and V T is the threshold voltage of M1 and M2.

As M1 and M2 form a differential pair, V FG1 ≈ V FG2

$$ V_{{{{FG}}2}} \approx k_{{{o}}} V_{{{{out}}}} + k_{{{{T}}2}} {\left( {\frac{{V_{{{T}}} }} {{k_{{{{T}}2}} }}} \right)} \approx {\sum\limits_{i = 1}^n {k_{i} V_{i} + k_{{{{T}}1}} {\left( {\frac{{V_{{{T}}} }} {{k_{{{{T}}1}} }}} \right)}} } $$
(6)

where V FG2 is the floating gate potential of M2, k T2 = C T2/C Total2 and k o  = C o /C Total2, C T2, C o and C Total2 being the capacitive coupling coefficients of the respective control gates of M2 and total capacitance of M2, respectively.

Equation 6 can be simplified as

$$ V_{{{{out}}}} \approx \frac{1} {{k_{{{o}}} }}{\sum\limits_{i = 1}^n {k_{i} V_{i} } } $$
(7)

Or,

$$ V_{{{{out}}}} \approx \frac{1} {{k_{{{o}}} C_{{{{Total}}1}} }}{\sum\limits_{i = 1}^n {C_{i} V_{i} } } $$
(8)

If the die is designed to have

$$ C_{i} = \frac{{C_{{{{FG}}}} }} {{2^{i} }} $$
(9)

then Eq. 8 becomes

$$ V_{{{{out}}}} \approx \frac{{C_{{{{FG}}}} }} {{k_{{{o}}} C_{{{{Total}}1}} }}{\sum\limits_{i = 1}^n {\frac{{V_{i} }} {{2^{i} }}} } $$
(10)

where C FG is the common factor with a suitable value.

4 Low voltage D/A converter

The structure of DAC shown in Fig. 2 has been modified by using a low voltage current mirror proposed in [11], and the resultant circuit for the low voltage D/A converter (LV DAC) is shown in Fig. 3. To drive M3 in saturation, M6 is biased in sub-threshold region by selecting I bias1 at sufficiently low level. M6 acts as a level shifter, reducing the minimum voltage drop across the current mirror. This arrangement reduces the power supply requirements of the D/A converter, thereby reducing the power consumption.

Fig. 3
figure 3

Proposed n-bit low voltage DAC

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5 Simulation results

SPICE simulations using 0.13 μm CMOS technology were carried out to validate the operation of both the DAC circuits and evaluate their performance characteristics [12]. The simulations were run at 100 M samples/s.

It may be noted that application of inputs V T /k T1 and V T /k T2 at the gates M1 and M2, respectively, is optional. But it was found through simulation that application of these two inputs removes the transition glitches that were found to be present in the circuit’s response, thereby reducing the static non-linearities.

5.1 Proposed DAC

The circuit was operated at a power supply voltage of ±2.5 V, whereas digital LOW and HIGH voltage levels were 0 and 1.5 V and I bias was 100 μA. The output response for the 8-bit DAC is shown in Fig. 4. As seen in Fig. 5, a good accuracy is achieved, and the performance parameters INL and DNL were found to be around 0.43 LSB each. The circuit was found to possess an offset error of 25.22 mV and a full scale gain error of 0.071 V. Simulated values of other performance indices are presented in Table 1.

Fig. 4
figure 4

DAC output voltage

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Fig. 5
figure 5

Static performance of DAC (a) Differential non-linearity (b) Integrated non-linearity

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Table 1 Summary of simulation results
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5.2 LV DAC

The DC output voltage and static linearities for an 8-bit LV DAC are shown in Figs. 6 and 7, respectively. The LV DAC can be operated at a power supply voltage of ±1 V, with the digital LOW and HIGH voltage levels being 0 and 0.5 V. The bias currents, I bias1, I bias2 and I bias3, were set at 10 nA, 20 μA and 100 μA, respectively. The INL and DNL for this circuit have been found to be 0.5 LSB. A comparison of its simulated performance with the proposed DAC is provided in Table 1.

Fig. 6
figure 6

LV DAC output voltage

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Fig. 7
figure 7

Static performance of LV DAC (a) Differential non-linearity (b) Integrated non-linearity

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6 Conclusion

A new D/A conversion circuit architecture using floating gate MOSFETs has been presented. The scheme exploits the property of weighted summation of gate-voltages, with capacitive coupling ratios as weighting coefficients. The proposed structure possesses good accuracy and low power consumption which have been verified using SPICE simulations of 8-bit version. The power consumption and supply requirements can be further compressed by employing a low voltage current mirror, without much effect on the performance. Due to their simple structures, the proposed DACs are suitable for complex on-chip mixed-signal circuit blocks.