Abstract
Receiver design challenges arising from new GNSS signals include required intermediate frequency, sampling rate, modulation type, spreading code, and secondary code. Several architectures are examined here aiming at a best model for multi-GNSS implementation, especially the underlying baseband and software realization platform. In this pursuit, it is found that the multi-core and multiple processor architectures are promising candidates. General purpose processors or digital signal processors demand excessive resources and power consumption. Alternative architectures are presented along with the general cost function, used to evaluate architecture efficiency. Taking into account (1) the superiority of a hardware time-interleaving technique, (2) RAM-based design versus register-based design, and (3) careful consideration of modern GNSS signal attributes, the proposed programmable custom pipeline correlator core provides flexibility and significantly reduces resources and power.
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Tran, V.T., Shivaramaiah, N.C. & Dempster, A.G. Feasibility analysis of baseband architectures for multi-GNSS receivers. GPS Solut 21, 1–11 (2017). https://doi.org/10.1007/s10291-016-0542-0
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DOI: https://doi.org/10.1007/s10291-016-0542-0