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Physics based analytical modeling and simulation of Cylindrical Junctionless Nanowire Ferroelectric field effect transistor (CJNFe-FET) for enhanced analog performance

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Abstract

An analytical model has been examined in this work for dielectric engineered gate stack high K cylindrical junctionless nanowire ferrolectric field effect transistor (HCJNFe FET). HCJNFe FET (High K junctionless nanowire ferrolectric field effect transistor) modulated with high K dielectric HfO2 has been compared with Conventional CJNFe FET (cylindrical junctionless nanowire field effect transistor). It has been illustrated that HCJNFe FET exhibits much higher efficiency than the traditional CJNFe FET and possess excellent device performance, including low sub-threshold slope, low leakage currents, increased drain current, better transconductance gm, output conductance gd, Ion/Ioff ratio, cutoff frequency, gain frequency product (GFP), Gain transconductance frequency product (GTFP), intrinsic gain, etc. Thus, the device is suitable for high frequency applications and also for low power digital applications. The proposed device also showed moderate linearity performance for various parameters like second order harmonics (gm2), third order harmonics (gm3), extrapolated input power (IIP2), voltage intercept point (VIP2), voltage intercept point (VIP3), Intermodulation distortion (IMD3). The parabolic approximation of potential is used to predict drain current model in different operating region. Landau Khalatnikov model is used to explain the negative capacitance phenomenon because of which subthreshold slope can be reduced below 60 mV/dec. Due to negative capacitance phenomenon internal voltage amplification take place. Thus, the value of threshold voltage has been reduced. The simulated results using ATLAS 3-D simulator are coherent with the analytical results produced from the model.

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Acknowledgements

Authors are gratified to the Director, Maharaja Agrasen Institute of Technology for providing necessary facilities to carry out this research work.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, Kashmere Gate, New Delhi, 110006, India

    Shalu Garg & Jasdeep Kaur

  2. Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, New Delhi, 110086, India

    Anubha Goel & R. S. Gupta

  3. Department of Physics, Motilal Nehru College, University of Delhi, New Delhi, 110021, India

    Subhasis Haldar

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  1. Shalu Garg
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  2. Jasdeep Kaur
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  3. Anubha Goel
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  4. Subhasis Haldar
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  5. R. S. Gupta
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Correspondence to Shalu Garg.

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Garg, S., Kaur, J., Goel, A. et al. Physics based analytical modeling and simulation of Cylindrical Junctionless Nanowire Ferroelectric field effect transistor (CJNFe-FET) for enhanced analog performance. Microsyst Technol 29, 1417–1429 (2023). https://doi.org/10.1007/s00542-023-05468-z

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