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Signal aware energy efficient approach for low power full adder design with adiabatic logic

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Abstract

Prolonged battery life is the major concern for modern low power electronic devices. Concentrating on this issue, in this paper a new structure of full adder has been proposed. Based on this architecture four new designs of low power full adder have been proposed. Two designs of proposed full adder i.e., A1 and A3 consist of four and three transistors based X-NOR gate respectively. Functionality of these two designs also verified with improved performance by employing diode free adiabatic logic (DFAL) in proposed adders, A2, and A4. Signal aware power efficient inverters have been used for proposed designs. Proposed adder designs are fast and consume less power as compared to the existing adders reported in literature. The proposed designs show a power delay product (PDP) of 0.041 fJ, 0.016 fJ, 0.054 fJ, and 0.047 fJ for adder A1, A2, A3 and, A4 respectively as compared to best reported double pass transistor full adder with 0.061 fJ. The proposed designs also perform well at stringent temperature, capacitance and, frequency conditions. These designs show satisfactory performance at low voltages whereas; the use of adiabatic logic makes these designs energy efficient for low power applications.

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Authors and Affiliations

  1. USIC&T, Guru Gobind Singh Indraprastha University, Sec-16C, Dwarka, New Delhi, 110078, India

    Dinesh Kumar & Manoj Kumar

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  1. Dinesh Kumar
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  2. Manoj Kumar
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Correspondence to Dinesh Kumar.

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Kumar, D., Kumar, M. Signal aware energy efficient approach for low power full adder design with adiabatic logic. Microsyst Technol 28, 587–599 (2022). https://doi.org/10.1007/s00542-020-05056-5

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  • DOI: https://doi.org/10.1007/s00542-020-05056-5

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