Abstract
This paper presents the comparative analysis of average power dissipation for conventional CMOS and different adiabatic logic techniques like efficient charge recovery logic (ECRL) and positive feedback adiabatic logic (PFAL) based digital circuits like inverter, NAND, NOR, 2:1 MUX, EXOR, and full adder. These circuits are based on reversible logic that works on AC power supply which can be trapezoidal or sinusoidal voltage source. The analysis of average power and delay is carried out at 180, 90, and 45 nm technology files for different frequencies. The result shows the significant reduction in power dissipation up to 26, 36, 16, 59, 73, 99% for inverter, NAND gate, NOR gate, EXOR gate, 2:1 MUX, and full adder circuits, respectively with adiabatic logic comparatively CMOS within specified frequency range of 1 kHz to 1 MHz and also manifests till what extent the power can be reduced so as to avoid degradation in performance. The design and simulation are performed on cadence virtuoso EDA tool.
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Mani, B., Gupta, S., Kumar, H. (2020). Adiabatic Design Implementation of Digital Circuits for Low Power Applications. In: Sharma, D.K., Balas, V.E., Son, L.H., Sharma, R., Cengiz, K. (eds) Micro-Electronics and Telecommunication Engineering. Lecture Notes in Networks and Systems, vol 106. Springer, Singapore. https://doi.org/10.1007/978-981-15-2329-8_28
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DOI: https://doi.org/10.1007/978-981-15-2329-8_28
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