Modern wireless transceivers require multi-band and multi-standard operation, which leads to complex, bulky and power hungry implementations. An architecture for state-of-the-art multi-standard transceiver is shown in Fig. 1, where several transmitter (TX) and receiver (RX) chains are required in order to fulfill specifications for wireless standards.
With the evolution of wireless systems, even more communication standards are being proposed while maintaining backward compatibility, therefore, cost and complexity of RF transceivers tend to increase. For high-performance communication standards, external off-chip components with optimized performance such as duplexer filter and power amplifier (PA), are necessary to satisfy ever-growing standard requirements. On the contrary, for low-performance battery operated applications such as Internet of things (IoT), low-power and low-cost implementations are desired.
This article presents a set of innovative design concepts, for receivers, transmitters and system-in-package (SiP) integration, which provides reconfigurability, wide frequency operation, higher power efficiency and low-cost. Based on the presented concepts, an RF transceiver architecture shown in Fig. 2 is proposed. The RX chain is based on a tunable active-balun LNA and a sub-sampling down-conversion mixer with discrete-time signal processing (DTSP). The transmitter is realized as a high-efficiency digital power amplifier (DPA) working as RF-DAC. Finally, a SiP integration provides high-quality, low-cost passive components for matching network and duplexer implementation.
The whole transceiver architecture is thought to be designed in a single-chip, avoiding cost increase caused by a multi-chip solution. A tunable-band LNA relaxes the linearity requirements of wideband LNAs, and the programmable gain fulfills the sensitivity requirements of various wireless standards. Ideal software defined radio (SDR) concept relies on a analog-to-digital converter (ADC) to digitize the RF signal immediately after the antenna and transfer the complete signal processing to the digital domain [1]. For example, for a Nyquist ADC with 2 GHz RF input signal, a sampling frequency of 4 GSps is necessary with high enough resolution. These stringent specifications are currently not practical for battery operated low-power applications. The sampling receivers provide a step towards this goal by employing discrete-time signal processing with additional flexibility [4, 5, 11, 13]. Receiver implementations in [4, 13] focus on oversampling the RF signal to place the images above the center frequency. The tuned receiver in [11] samples the 2.4 GHz RF signal at a very low sampling frequency of 100 MHz resulting in very high noise figure of 21 dB due to noise folding. The implementation [5] utilize bandpass sampling theory to optimize the sampling frequency of 1.07 GHz for 2.4 GHz RF signal but lacks the front-end LNA. The proposed sub-sampling receiver architecture utilizes sub-sampling mixer followed DTSP after the front-end LNA. Use of sub-sampling leads to lower local oscillator frequency, less-complex frequency synthesizer and lower power consumption compared to traditional all analog receivers.
An RF-DAC unites in one block the functionality of a digital-to-analog converter (DAC), up-conversion and amplification stages. It has the advantage of higher efficiency when compared to traditional analog PAs and can be integrated in standard CMOS technology. An electric balance duplexer (EBD) can be fully integrated in a SiP and prevents the use of external costly duplexer. SiP transformers can be used in the matching network (MN) and Duplexer as an alternative to CMOS transformers. They reduce the production cost and additionally contribute to a more efficient RF-DAC and low loss duplexer structures.
The rest of article is organized as follows, in Sect. 2 a review about sub-sampling receivers will be presented with LNA implementation details. In Sect. 3 a review and analysis of a DPA will be presented. In Sect. 4 implementation and measurement results of on-package transformers for duplexer and MN will be shown. In Sect. 5 recently proposed solutions for integrated duplexers, its advantages and limitations will be discussed. Section 6 presents conclusions and final considerations of the proposed transceiver.