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Design of tunnel FET architectures for low power application using improved Chimp optimizer algorithm

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Abstract

An improved Chimps optimizer algorithm is proposed in this paper and is applied for the performance optimization of tunnel FET architectures for use in low power VLSI circuits. The steep subthreshold characteristics of TFET improves device performance and make it suitable for low power digital and memory applications. Classical Chimps optimizer has poor convergence and problem to stuck into local minima for high dimensional problems. This research focuses on mathematical model of divergent thinking and sensual movement of chimps in four different forms named attacker, barrier, chaser, and driver for simulation. The improved variant of Chimps optimizer has been proposed in this research and named as Imp-Chimp. To validate the efficacy and feasibility of the suggested technique, it has been examined for standard benchmarks and multidisciplinary engineering design problems to solve non-convex, non-linear, and typical engineering design problems. The suggested technique variants have been evaluated for seven standard unimodal benchmark functions, six standard multi modal benchmark functions, ten standard fixed dimension benchmark functions and engineering design problems (i. e., TFET, BTBT). The outcomes of this method have been compared with other existing optimization methods considering convergence speed as well as for searching local and global optimal solutions. The testing results show the better performance of the proposed method. The paper also demonstrates the tunnel field effect transistor (TFET) as a promising device for low power electronic circuits and an engineering problem where the Imp-Chimp optimizer can be implemented for performance improvement. The TFET is based on the carrier generation using the quantum mechanical process of the band-to-band tunneling (BTBT). TFET can meet the requirements of a device that can perform on low supply voltage with reduced leakage currents and low sub-threshold swing. TFET can be optimized to give similar performance as MOSFET, but with much lower power consumption.

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Acknowledgements

We acknowledge for the support and lab facility provided by School of Electronics and Electrical Engineering, Lovely Professional University, Punjab India.

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  1. School of Electronics and Electrical Engineering, Lovely Professional University, Punjab, India

    Sabitabrata Bhattacharya, Suman Lata Tripathi & Vikram Kumar Kamboj

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  1. Sabitabrata Bhattacharya
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Glossary

GOSC TFET

Gate on source channel tunnel field effect transistor [120]

SiGe-S-NW-TFET

SiGe source nano wire tunnel field effect transistor [121]

HGD DE DMG DL TFET

Hetero gate dielectric drain engineered dual metal gate tunnel field effect transistor [122]

HGD DW TFET

Hetero gate dielectric dual gate-metal work function tunnel field effect transistor [124]

GDO– HD–GAA-TFET

Gate drain overlapped hetero gate dielectric gate all around tunnel field effect transistor [123]

U HJ VTFET

U-shaped gate hetero junction vertical tunnel field effect transistor [126]

DMCG-CPTFET

Dual metal control gate charge plasma tunnel field effect transistor [130]

V-DMTFET

Vertical dielectric modulated tunnel field effect transistor [140]

HM-GUL-ED-TFET

Hetero material gate underlapped electrically doped tunnel field effect transistor [131]

D GAA CS NT TFET

Dual gate all around core shell nano tube tunnel field effect transistor [129]

JL-TFET

Junction less tunnel field effect transistor [132]

SD-SG TFET

Splitted drain single gate tunnel field effect transistor [135]

VS-TFET

Vertical sandwiched channel tunnel field effect transistor [127]

DE-QG-TFET

Drain engineered quadruple gate tunnel field effect transistor [128]

JLSGTFET

Junction less single gate tunnel field effect transistor [133]

GSHJ-PGP-STFET

Ge source hetero junction partial ground plane base SELBOX (selective buried oxide) tunnel field effect transistor [139]

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Bhattacharya, S., Tripathi, S.L. & Kamboj, V.K. Design of tunnel FET architectures for low power application using improved Chimp optimizer algorithm. Engineering with Computers 39, 1415–1458 (2023). https://doi.org/10.1007/s00366-021-01530-4

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