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High-speed SOI junctionless transistor based on hybrid heterostructure of Si/Si0.5Ge0.5 and asymmetric spacers with outstanding analog/RF parameters

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Abstract

In junctionless (JL) transistors, impurity scattering limits the carrier velocity within a channel, disturbing its performance in analog/RF applications. For the first time, the Si/Si0.5Ge0.5 heterostructures and asymmetric spacers are used in this paper to improve the figures of merit of analog/RF performance of a silicon-on-insulator JL transistor (SOI-JLT). The proposed device is called hybrid heterostructure-SOI-JLT (HH-SOI-JLT), in which regions with HfO2 are referred to as the high-κ spacer, whereas regions with SiO2 are known as the low-κ spacer. According to the simulation results, Si/Si0.5Ge0.5 heterostructure in the channel of the HH-SOI-JLT device caused an offset in the conduction band energy and created quantum well in the interfacial of drain/channel and enhanced electron velocity and density of electrons significantly. Moreover, using the high-κ spacer intensified the fringing fields in the region above the threshold, and using the low-κ spacer decreased the gate-to-drain capacitance. With a 20-nm channel, maximum transconductance (Gmmax), unity gain cut-off frequency (\(f_{T}\)), and intrinsic gain (AV) of the HH-SOI-JLT device are optimized by 265%, 83%, and 90%, respectively, compared to the same dimensional SOI-JLT device. In fact, the proposed HH-SOI-JLT device can be an appropriate candidate for analog/RF applications.

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Authors and Affiliations

  1. Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran

    Mohammad Fallahnejad

  2. Department of Electrical Engineering, College of Technical and Engineering, West Tehran Branch, Islamic Azad University, Tehran, Iran

    Amir Amini & Amir Khodabakhsh

  3. Department of Electrical Engineering, Karaj Branch, Islamic Azad University, Karaj, Iran

    Mahdi Vadizadeh

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  1. Mohammad Fallahnejad
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  2. Amir Amini
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  4. Mahdi Vadizadeh
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Correspondence to Amir Amini.

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Fallahnejad, M., Amini, A., Khodabakhsh, A. et al. High-speed SOI junctionless transistor based on hybrid heterostructure of Si/Si0.5Ge0.5 and asymmetric spacers with outstanding analog/RF parameters. Appl. Phys. A 128, 47 (2022). https://doi.org/10.1007/s00339-021-05153-w

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