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Non-volatile memory effect of a high-density NiSi nano-dots floating gate memory using single triangular-shaped Si nanowire channel

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Abstract

A back-gated nonplanar floating gate device based on buried single triangular-shaped Si nanowire channel (width ∼40 nm) and embedded high-density uniform NiSi nano-dots (∼1.5×1012 cm−2) is demonstrated. Memory properties including memory window, programming/erasing, and retention are evaluated. The transfer and transient characteristics show clear charge injection, storage and removal effects and the associated programming/erasing mechanism based on fringing electric field is studied. Robust room and high temperature retention performance is observed.

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Acknowledgements

This material is based on research sponsored by DARPA/Defense Microelectronics Activity (DMEA) under agreement number H94003-10-2-1003 and the National Science Foundation (NSF) DMR-0807232.

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Authors and Affiliations

  1. Quantum Structures Laboratory, Department of Electrical Engineering, University of California, Riverside, CA, 92521, USA

    Jingjian Ren, Sheng Chu & Jianlin Liu

  2. Center for Nanoscale Science and Engineering, University of California, Riverside, CA, 92521, USA

    Dong Yan

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  1. Jingjian Ren
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  2. Dong Yan
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  3. Sheng Chu
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  4. Jianlin Liu
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Correspondence to Jianlin Liu.

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Ren, J., Yan, D., Chu, S. et al. Non-volatile memory effect of a high-density NiSi nano-dots floating gate memory using single triangular-shaped Si nanowire channel. Appl. Phys. A 111, 719–724 (2013). https://doi.org/10.1007/s00339-013-7641-3

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