Abstract
The optimized pure hardware fixed-point implementation of the active disturbance rejection control algorithm on the field programmable gate array (FPGA) is presented in this paper. The optimization of the FPGA resource occupancy is provided with the simulation-based algorithm refinement, the selection of the optimal hardware structure and the modularity principle. In contrast to the conventional very high speed integrated circuit hardware description language (VHDL) approach, the implementation of the proposed optimal hardware design is realized by the system-level design tool, i.e. Xilinx’s System Generator\(^{\mathrm{TM}}\) (XSG). Our methodology demonstrates distinct advantages such as the shorter development time and a simpler optimization procedure of the FPGA resource occupancy. Further, automatically converting the specified XSG model into the VHDL code significantly reduces the coding efforts. The experimental results largely coincide with the simulations and confirm satisfactory system performances in the different working conditions.
Similar content being viewed by others
References
Han J (2009) From PID to active disturbance rejection control. IEEE Trans Ind Electron 56(3):900–906. doi:10.1109/TIE.2008.2011621
Feng G, Liu YF, Huang L (2004) A new robust algorithm to improve the dynamic performance on the speed control of induction motor Drive. IEEE Trans Power Electron 19(6):1614–1627. doi:10.1109/TPEL.2004.836619
Przybyła M, Kordasz M, Madoński R, Herman P, Sauer P (2012) Active Disturbance Rejection Control of a 2DOF manipulator with significant modeling uncertainty. Bull Polish Acad Sci Techn Sci 60(3):509–520. doi:10.2478/v10175-012-0064-z
Vincent J, Morris D, Usher N, Gao Z, Zhao S, Nicoletti A, Zheng Q (2011) On active disturbance rejection based control design for superconducting RF cavities. Nuclear Instrum Methods Phys Res A 643:11–16. doi:10.1016/j.nima.2011.04.033
Xia Y, Dai L, Fu M, Li C, Wang C (2014) Application of active disturbance rejection control in tank gun control system. J Frankl Inst 351(4):2299–2314. doi:10.1016/j.jfranklin.2013.02.003
Huang Y, Xue W (2014) Active disturbance rejection control: methodology and theoretical analysis. ISA Trans 53(4):963–976. doi:10.1016/j.isatra.2014.03.003
Dubey R (2009) Introduction to embedded system design using field programmable gate arrays. Springer, London
Hsu F, Lee B (2011) FPGA-based adaptive PID control of a DC motor driver via sliding-mode approach. Expert Syst Appl 38:11866–11872. doi:10.1016/j.eswa.2011.02.185
Hasanien HM (2011) FPGA implementation of adaptive ANN controller for speed regulation of permanent magnet stepper motor drives. Energy Convers Manag 52(2):1252–1257. doi:10.1016/j.enconman.2010.09.021
Astarloa A, Lázaro J, Bidarte U, Jiménez J, Zuloaga A (2009) FPGA technology for multi-axis control systems. Mechatronics 19(2):258–268. doi:10.1016/j.mechatronics.2008.09.001
Martinez M, Franco A, Herrera G, Soto O (2013) Multi-axis motion controller for robotic applications implemented on an FPGA. Int J Adv Manuf Technol 67:2367–2376. doi:10.1007/s00170-012-4656-4
Monmasson E, Cirstea M (2007) FPGA design methodology for industrial control systems—a review. IEEE Trans Ind Electron 54(4):1824–1842. doi:10.1109/TIE.2007.898281
Fang Z, Carletta JE, Veillette RJ (2005) A methodology for FPGA-based control implementation. IEEE Trans Control Syst Technol 13(6):977–987. doi:10.1109/TCST.2005.857411
Constantinides G, Cheung P, Luk W (2004) Synthesis and optimization of DSP algorithms (Chapter 3: Peak value estimation). Kluwer Academic Publishers, New York
Sun B, Gao Z (2005) A DSP-based active disturbance rejection control design for a 1-kW H-bridge DC-DC power converter. IEEE Trans Ind Electron 52(5):1271–1277. doi:10.1109/TIE.2005.855679
Zhao S, Gao Z (2014) Modified active disturbance rejection control for time-delay systems. ISA Trans 53(4):882–888. doi:10.1016/j.isatra.2013.09.013
Zhang Y, Zhang Y, Wang J, Ma R (2013) An active disturbance rejection control of induction motor using DSP+FPGA. In: Proceedings of the IEEE 25th Chinese Control and Decision Conference (CCDC), pp 4047–4052. doi:10.1109/CCDC.2013.6561659
Tollies N (2007) A versatile high performance floating-point based integrated circuit design for active disturbance rejection control. Master thesis, Clevelend State University
Zheng Q, Dong L, Lee DH, Gao Z (2009) Active disturbance rejection control for MEMS gyroscopes. IEEE Trans Control Syst Technol 17(6):1432–1438. doi:10.1109/TCST.2008.2008638
Zhao S, Usher N, Morris D, Vincent J (2013) Fixed-point implementation of active disturbance rejection control for superconducting radiofrequency cavities. In: Proceedings of the IEEE American Control Conference (ACC), pp 2693–2698. doi:10.1109/ACC.2013.6580241
Stankovic M, Manojlovic S, Simic S, Jovanovic Z (2014) Implementation of active disturbance rejection control on FPGA. In: Presented at the International Conference on Electrical, Electronic and Computing Engineering (IcETRAN)
Gao Z (2003) Scaling and bandwidth-parameterization based controller tuning. In: Proceedings of the American Control Conference (ACC), vol 6, pp 4989–4996. doi:10.1109/ACC.2003.1242516
Franklin GF, Workman ML, Powell D (1997) Digital control of dynamic systems (Chapter 8: design using state-space methods), 3rd edn. Addison-Wesley Longman Publishing, Boston
Herbst G (2013) A simulative study on active disturbance rejection control (ADRC) as a control tool for practitioners. Electronics 2:246–279. doi:10.3390/electronics2030246
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Stankovic, M., Naumovic, M., Manojlovic, S. et al. Optimized pure hardware FPGA-based implementation of active disturbance rejection control. Electr Eng 100, 111–121 (2018). https://doi.org/10.1007/s00202-016-0495-x
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00202-016-0495-x