Abstract
The phase frequency detector (PFD) is an important component in a phase-locked loop (PLL). PFD detects the timing difference between the reference clock (REFCK) and the feedback clock (FBCK). PFD plays a major role in deciding the amount of time required by a PLL to achieve lock. The blind zone in the PFD causes inaccurate PFD output. This negatively impacts the PLL’s lock-in time. The increase in lock-in time poses great challenges for developing high-speed PLLs. This paper proposes a PFD architecture that eliminates the reset pulse when the timing difference between the REFCK and the FBCK is significantly high. The elimination of the reset pulse in this way leads to a blind zone free PFD across process, voltage, and temperature (PVT) variations. The PFD is realized and implemented in the Cadence spectre environment using the UMC 0.18 \(\upmu \)m CMOS process. From the results, it can be stated that the designed PFD is blind zone free across PVT variations. The proposed PFD-based PLL locks faster than the traditional PFD-based PLL. The proposed PFD consumes 163 \(\upmu \)W power at a 100 MHz operating frequency which is the lowest compared to the earlier reported works. Its operational range is [\(-2\pi ,2\pi \)]. The PFD occupies an area of 0.0069 \(\textrm{mm}^2\). The proposed design is well suited to low-power, high-speed PLL applications.
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The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.
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All authors reviewed the manuscript. Kumaravel Sundaram contributed to the study conception. The design and analysis were performed by Marichamy Divya. The first draft of the manuscript was written by Marichamy Divya, and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.
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Divya, M., Sundaram, K. Blind Zone-Less Phase Frequency Detector for a Low-Power Phase-Locked Loop Architecture. Circuits Syst Signal Process 42, 6399–6419 (2023). https://doi.org/10.1007/s00034-023-02413-3
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DOI: https://doi.org/10.1007/s00034-023-02413-3