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Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators

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Abstract

In order to improve the performance of deep neural network (DNN) accelerators, it is necessary to optimize compute efficiency and operating frequency. However, the implementation of contemporary DNNs often requires excessive resources due to the heavy multiply-and-accumulate (MAC) computations. In this work proposes a MAC unit designed with a Co-ordinate Rotation DIgital Computer (CORDIC)-based architecture, which is both power and area-efficient for 8-bit and higher-bit precision. The CORDIC-based designs are typically associated with low throughput. To address this issue, a performance-centric pipelined architecture is investigated that increases throughput. The study conducts a detailed Pareto analysis of accuracy variation at different precision levels and required pipeline stages to achieve high performance. The proposed MAC unit’s post-synthesis results at the 45nm technology node are provided, and performance is evaluated on a deep neural network using Vertex-7 FPGA board. The proposed fixed-point MAC architecture is scalable for all bit-precision and flexible for the decimal point implication. The study finds that the proposed Fixed Q\(_{3.5}\) precision with five pipeline stage-based MAC shows better performance metrics compared to the recursive CORDIC-based MAC design. The proposed MAC design has a lower area-delay-product (ADP) which is 1.13\(\times \), and higher throughput of 2.73\(\times \) compared to the recursive CORDIC-based MAC. The study evaluated the performance of the proposed MAC unit using the fully connected NN for the MNIST dataset and found that the throughput 1.89\(\times \) better compared to the conventional MAC-based design.

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Data Availability

Data sharing is not applicable to this article as no data sets were generated or analyzed during the current study, and detailed circuit simulation results are given in the manuscript.

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Acknowledgements

The authors would like to thank the University Grant Commission (UGC) New Delhi, Government of India under the SRF scheme with award no. 22745/(NET-DEC. 2015) for providing financial support. And Special Manpower Development Program Chip to System Design (SMDP), Department of Electronics and Information Technology (DeitY) under the Ministry of Communication and Information Technology, Government of India for providing necessary Research Facilities.

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Authors and Affiliations

  1. Department of Electrical Engineering, IIT Indore, Indore, India

    Gopal Raut, Jogesh Mukala & Santosh Kumar Vishvakarma

  2. Nanyang Technological University, Singapore, Singapore

    Vishal Sharma

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  1. Gopal Raut
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Correspondence to Santosh Kumar Vishvakarma.

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Raut, G., Mukala, J., Sharma, V. et al. Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators. Circuits Syst Signal Process 42, 6089–6115 (2023). https://doi.org/10.1007/s00034-023-02387-2

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