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Design of CNTFET-Based Ternary and Quaternary Magnitude Comparator

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Abstract

This paper presents a novel power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based design of a quaternary magnitude comparator for single and double digits. It also proposes an improved circuit of the ternary single-digit comparator and a novel design of the double-digit ternary comparator. The designs make use of the pass transistor logic and transmission gates, resulting in a more power and energy-efficient design with a lower number of CNTFETs when compared with existing designs. Besides, this paper also proposes a generalized circuit of magnitude comparator for multiple digits. The proposed circuits are simulated in HSPICE using the 32 nm CNTFET model presented by Stanford University. Average power and propagation delays are observed and the power-delay-product (PDP) is calculated in each case. The impact of process parameter variations has been analyzed through Monte Carlo simulation and has been presented in the form of two-dimensional graphs.

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  1. Department of Electronics and Communication Engineering, Techno India University, EM 4, Sector V, Salt Lake, Kolkata, West Bengal, 700091, India

    Anisha Paul & Buddhadev Pradhan

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  1. Anisha Paul
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Correspondence to Anisha Paul.

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Paul, A., Pradhan, B. Design of CNTFET-Based Ternary and Quaternary Magnitude Comparator. Circuits Syst Signal Process 42, 5634–5662 (2023). https://doi.org/10.1007/s00034-023-02380-9

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