Design of area, energy and security optimized reversible architectures for digital image cryptography

Abstract

Image data is frequently processed in multimedia, wireless, mobile communication etc. The digital images transmitted over the internet are prone to security threats and thus providing security for the images and videos becomes an essential issue for individuals, business and governments. Moreover, applications in the automobile, banking, medical, construction and fashion industry require designs, scanned data, and blue-prints to be protected against attackers. Though many cryptographic algorithms are proposed in literatures, there is no much effort concentrated on the design of low-power hardware-efficient cryptosystem architectures. In this work, we propose a novel crypto architecture using multiple Boolean reversible blocks with logic control inputs derived from standard test images. The pre-processing and shuffling on the control pixel bits decide the depth of logic operation of the crypto system. The proposed design involves Gray Code Image Scrambling block for pre-processing, Reversible Shuffling Unit for bit plane modification and final merger for plane regrouping and is designated as Reversible Logic-Image Key (RL-IK) design. The use of reversible logic unit for shuffling combined with Gray code image scrambling in key generation improves the security of the processed images from the encryption unit at the expense of increase in area. To optimize the proposed RL-IK design in terms of area and security metrics, Gray Code bit plane processing is eliminated in the least n/2–1 bits as the contribution of least significant bits in the pixel intensity is less. The proposed Area and Security Optimized RL-IK Architecture (AS-RL-IK) involves same process as that of its standard counterpart in n/2 + 1 Most Significant Bits bits. As the weight based shuffling block is the critical unit of the proposed architecture that contributes for high delay and hardware area, for portable non-critical applications high speed hardware efficient variant of RL-IK is proposed. The proposed High Speed Area Efficient RL-IK (HSAE-RL-IK) design eliminates the weight based shuffling unit and employs only the multi-logic reversible block to produce the intermediate cipher image. The proposed crypto systems are designed using structural Verilog HDL. Simulations with 180 nm and 45 nm Application Specific Integrated Circuit technology reveals that RLC-IK design and its optimized variants exhibits 37% less power consumption and 35% less delay than Integer Wavelet Transform-Heterogeneous Key Generation (IWT-HKG) design with optimized security to the least when compared to the best of designs.