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Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs

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Abstract

This paper analyzes high-speed front-end samplers and presents a 1 × 4 × 8 three-stage sampler for time-interleaved analog-to-digital converters. The front-end sampler mitigates timing skew and extends bandwidth by adopting global sampling and hierarchical demultiplexing. Inductive peaking is employed in both the track-and-hold amplifier and the inter-stage buffer amplifier to optimize the analog input bandwidth and flatten the amplitude–frequency response. Redundant branches and dummy devices are utilized to eliminate signal feedthrough and adjust common-mode voltages. The simulation results show that the signal-to-noise-and-distortion ratio of the proposed sampler running at 32 GS/s achieves 43.97 dB at 15.91 GHz and 48.67 dB at 26.18 GHz input frequencies, respectively. The total power consumption is 137.74 mW in a 65-nm CMOS technology.

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Data Availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

This work was supported by the National Natural Science Foundation of China (No. 61904133, 62090040, 62021004, 61961160703).

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Authors and Affiliations

  1. Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, 710071, China

    Jiale Ding, Yukai Huang, Dengquan Li, Shubin Liu, Yi Shen & Zhangming Zhu

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  1. Jiale Ding
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  2. Yukai Huang
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  3. Dengquan Li
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Correspondence to Dengquan Li.

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Ding, J., Huang, Y., Li, D. et al. Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs. Circuits Syst Signal Process 41, 6632–6650 (2022). https://doi.org/10.1007/s00034-022-02109-0

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