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High Efficient Polyphase Digital Down Converter on FPGA

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Abstract

This paper presents an implementation of a reconfigurable digital down converter (DDC) that can translate high sample rate to lower sample rate signal on field-programmable gate array (FPGA) platform using polyphase filtering. The proposed DDC consists of a polyphase mixer, a cascaded integrator comb (CIC) filter, and a finite impulse response (FIR) filter. The polyphase mixer reduces computational complexity and multiplier blocks simultaneously. Furthermore, the modified CIC filter improves the operating speed, and the new design method of the FIR filter saves memory storage to a great extent. The proposed structure is highly flexible so that the decimation factor can be programmed dynamically during runtime in terms of the sample rate, bandwidth, center frequency, and so on. Moreover, the optimum hardware description language (HDL) coding techniques significantly improve the area efficiency and speed performance of the DDC without compromising the functionality. The proposed design is synthesized using Xilinx Vivado 2020.2 and tested on a Xilinx Kintex-7 FPGA XC7K70T-FBG676 as the target device. Comparison results indicate that the proposed design substantially reduces the resources as well as power. A verification test is to certify the feasibility and correctness of the hardware implementation. The proposed DDC is well-matched in any digital radio application.

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Acknowledgements

The authors are expressed their sincere gratitude to MAKAUT for providing the valuable Xilinx Vivado Design Suite 2020.2 and FPGA board.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, MAKAUT, Nadia, Kolkata, India

    Debarshi Datta

  2. Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Nadia, India

    Himadri Sekhar Dutta

Authors
  1. Debarshi Datta
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  2. Himadri Sekhar Dutta
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Contributions

All the authors listed on the title page have contributed significantly to the work, have read the manuscript, attest to the validity and legitimacy of the data and its interpretation, and agree to its submission. The first author has prepared the proposed architecture, tables, figures, results, and body of the manuscript. The second author or co-author describes the abstract, literature survey discussion, and conclusion sections. Both authors read and approved the final manuscript.

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Correspondence to Debarshi Datta.

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Datta, D., Dutta, H.S. High Efficient Polyphase Digital Down Converter on FPGA. Circuits Syst Signal Process 40, 5787–5798 (2021). https://doi.org/10.1007/s00034-021-01749-y

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