Skip to main content
SpringerLink
Log in

Evaluating a Methodology for Designing CNFET-Based Ternary Circuits

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

A methodology for designing ternary circuits is proposed and evaluated. The method is based on a schema that consists of voltage levels, conditional blocks and weighting elements. The main idea is selecting appropriate voltage levels in conditional blocks and weighting them to generate desired output. In fact, the diagram is a framework for designing ternary logic gates. Hence, the optimum design can be accomplished by choosing the proper strategy particularly in conditional blocks. This could lead to minimum count of elements and decrement in complexity of the circuit. To examine the efficiency of the proposed method, three designs for standard ternary inverter (STI), ternary NAND (TNAND) and ternary NOR (TNOR) gates in carbon nanotube field-effect-transistor (CNFET) technology are presented, respectively. Several simulations are done using Synopsys HSPICE tool in 32 nm CNFET technology to measure the performance parameters for proposed designs and state-of-the-art CNFET-based designs. Moreover, the robustness of STIs in different operational conditions such as variations frequency and output load, and their senility to process deviations are measured. The simulation is done for TNAND, TNOR and half adder cell as well. The results demonstrate the proper functionality of the proposed methodology. Moreover, the designed circuits benefit from the minimum count of CNFETs, least maximum equivalent input capacitor, minimum variety of CNT diameters and delay time, while its pdp is very close to best results in comparison with state-of-the-art designs.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. E. Abiri, A. Darabi, A novel design of low power and high read stability ternary SRAM (T-SRAM), memory based on the modified gate diffusion input (m-GDI) method in nanotechnology. Microelectron. J. 58, 44–59 (2016)

    Article  Google Scholar 

  2. A. Anand, A. Islam, CNFET-based ternary inverter and its variability analysis, in Proceedings of 3rd International Conference on Reliability Infocom Technologies and Optimization (2014), pp. 1–6

  3. S. Angizi, F. Danehdaran, S. Sarmadi, S. Sheikhfaal, An ultra-high speed and low complexity quantum-dot cellular automata full adder. J. Low Power Electron. 11(2), 173–180 (2015)

    Article  Google Scholar 

  4. S. Bala, M. Khosla, Design and performance analysis of low-power SRAM based on electrostatically doped tunnel CNTFETs. J. Comput. Electron. 18, 856–863 (2019)

    Article  Google Scholar 

  5. N.H. Bastani, M.H. Moaiyeri, K. Navi, Carbon nanotube field effect transistor switching logic for designing efficient ternary arithmetic circuits. J. Nanoelectron. Optoelectron. 12(2), 118–129 (2017)

    Article  Google Scholar 

  6. G. Cho, F. Lombardi, A novel and improved design of a ternary CNTFET-based cell, in GLSVLSI’13, Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI (2013), pp. 131–136

  7. J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region. IEEE Trans. Electron Device 54(12), 3186–3194 (2007)

    Article  Google Scholar 

  8. J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Device 54(12), 3195–3205 (2007)

    Article  Google Scholar 

  9. A. Doostaregan, M.H. Moaiyeri, K. Navi, O. Hashemipour, On the design of new low-power CMOS standard ternary logic gates, in Proceedings of the 15th CSI International Symposium on Computer Architecture and Digital Systems (2010), pp. 115–120

  10. S.A. Ebrahimi, M.R. Reshadinezhad, A. Bohlooli, M. Shahsavari, Efcient CNTFET-based design of quaternary logic gates and arithmetic circuits. Microelectron. J. 53, 156–166 (2016)

    Article  Google Scholar 

  11. G. Hills, C. Lau, A. Wright, S. Fuller, M.D. Bishop, T. Srimani, P. Kanhaiya, R. Ho, A. Amer, Y. Stein, D. Murphy, A. Chndrakasan, M.M. Shulaker, Modern microprocessor built from complementary carbon nanotube transistors. Nature 572, 595–602 (2019)

    Article  Google Scholar 

  12. S.L. Hurst, Multiple-valued logic-its status and its future. IEEE Trans. Comput. 33(12), 1160–1179 (1984)

    Article  Google Scholar 

  13. S. Karmakar, A. Chandy, F.C. Jain, Design of ternary logic combinational circuits based on quantum dot gate FETs. IEEE Trans. Very Large Scale Integr. Syst. 21, 793–806 (2013)

    Article  Google Scholar 

  14. M.R. Khezeli, A. Jalali, M.H. Moaiyeri, On the impacts of process and temperature variations on the crosstalk effects in MWCNT bundle nanointerconnects in ternary logic. IEEE Trans. Nanotechnol. 17(2), 238–249 (2018)

    Article  Google Scholar 

  15. M.R. Khezeli, M.H. Moaiyeri, A. Jalali, Active shielding of MWCNT bundle interconnects: an efficient approach to cancellation of crosstalk-induced functional failures in ternary logic. IEEE Trans. Electromagn. Compat. 61(1), 100–110 (2019)

    Article  Google Scholar 

  16. M.R. Khezeli, M.H. Moaiyeri, A. Jalali, Comparative analysis of simultaneous switching noise effects in MWCNT bundle and Cu power interconnects in CNTFET-based ternary circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(1), 37–46 (2019)

    Article  Google Scholar 

  17. Y. Li, M. Droste, L. Lei, Model checking of linear-time properties in multi-valued systems. Inf. Sci. 377, 51–74 (2017)

    Article  Google Scholar 

  18. J. Liang, L. Chen, J. Han, F. Lombardi, Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs. IEEE Trans. Nanotechnol. 13(4), 695–708 (2014)

    Article  Google Scholar 

  19. S. Lin, Y.B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011)

    Article  Google Scholar 

  20. M. Maleknejad, S. Mohammadi, S.M. Mirhosseini, K. Navi, H.R. Naji, M. Hosseinzadeh, A low-power high-speed hybrid multi-threshold full adder design in CNFET technology. J. Comput. Electron. 17(3), 1257–1267 (2018)

    Article  Google Scholar 

  21. D.M. Miller, M.A. Thornton, Multiple valued logic: concepts and representations. Synth. Lect. Digit. Circ. Syst. 2(1), 1–127 (2007)

    Google Scholar 

  22. M.H. Moaiyeri, R.F. Mirzaee, A. Doostaregan, K. Navi, O. Hashemipour, A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. IET Comput. Digit. Tech. 7(4), 167–181 (2013)

    Article  Google Scholar 

  23. M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Devices Syst. 5(4), 285–296 (2011)

    Article  Google Scholar 

  24. S.L. Murotiya, A. Gupta, Design of high speed ternary full adder and three input XOR circuits using CNFETs, in Proceedings of the IEEE International Conference on VLSI Design (2015), pp. 292–297

  25. K. Pilarczyk, E. Wlazlak, D. Przyczyna, A. Blachecki, A. Podborska, V. Anathasiou, Z. Konkoli, K. Szaciłowski, Molecules, semiconductors, light and information: towards future sensing and computing paradigms. Coord. Chem. Rev. 365, 23–40 (2018)

    Article  Google Scholar 

  26. A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4, 168–179 (2005)

    Article  Google Scholar 

  27. S.K. Sahoo, G. Akhilesh, R. Sahoo, M. Muglikar, High performance ternary adder using CNTFET. IEEE Trans. Nanotechnol. 16(03), 368–374 (2017)

    Article  Google Scholar 

  28. S. Shin, E. Jang, J.W. Jeong, B.G. Park, K.R. Kim, Compact design of low power standard ternary inverter based on OFF-state current mechanism using nano-CMOS technology. IEEE Trans. Nanotechnol. 62(8), 2396–2403 (2015)

    Google Scholar 

  29. K.C. Smith, The prospects for multivalued logic: a technology and applications view. IEEE Trans. Comput. 30(9), 619–634 (1981)

    Article  MathSciNet  Google Scholar 

  30. N.S. Soliman, M.E. Fouda, A.G. Radwan, Memristor-CNTFET based ternary logic gates. Microelectron. J. 72, 74–85 (2018)

    Article  Google Scholar 

  31. H.T. Tari, A.D. Zarandi, M.R. Reshadinezhad, Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders. Microelectron. Eng. 215, 110980 (2019)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. School of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran

    Akbar Doostaregan & Adib Abrishamifar

Authors
  1. Akbar Doostaregan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Adib Abrishamifar
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Adib Abrishamifar.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Doostaregan, A., Abrishamifar, A. Evaluating a Methodology for Designing CNFET-Based Ternary Circuits. Circuits Syst Signal Process 39, 5039–5058 (2020). https://doi.org/10.1007/s00034-020-01400-2

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-020-01400-2

Keywords

Search

Navigation