Low-Power, Low-Area Multi-level 2-D Discrete Wavelet Transform Architecture

Abstract

This paper introduces an efficient, low-power, low-area multi-level 2-D discrete Haar wavelet transform (2-D DHWT) architecture. The proposed architecture consists of four add/subtract elements, register bank, three multiplexers and a buffer memory. All or fractions of the N-stage register are used to perform row–column image transposition for every 2-D DHWT decomposition level. A fixed size block memory of $\frac{{{\varvec{N}}}}{{{\varvec{2}}}}\times \frac{{{\varvec{N}}}}{{{\varvec{2}}}}$-sample is used to store low–low frequency band to perform multi-level 2-D DHWT decomposition, except for the first level where no block memory is used. For synthesis results, the proposed architecture outperforms similar architectures in hardware usage, power consumption and speed. Also, it is found that the power delay product of the proposed architecture is less than 1 $(\hbox {mW} \times \upmu \hbox {s})$ compared with up to 1.9 $(\hbox {mW} \times \upmu \hbox {s})$ for cascaded architecture. Furthermore, an up to 209 MHz processing speed is achieved which enables a three-level 2-D DHWT decomposition of a $256\times 256$-pixel image to be performed within 0.4 ms.