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High-Throughput Architectures for Circular Block-Type Low-Density Parity-Check Codes

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Abstract

This paper proposes applying a modified quasicyclic low-density parity-check, named as circular block-type LDPC (CB-LDPC), to a wireless communication system to improve the accuracy of received data. The CB-LDPC Matrix H is a circular and irregular matrix that uses the min-sum algorithm for iterative decoding calculations. It adopts bit node processing units, check node processing units, and buffers for a parallel design of a hardware structure with low complexity and a throughput of up to 1.1 Gbps.

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Acknowledgments

This study was partially supported by the Ministry of Science and Technology (MOST), Taiwan, under Grant NSC 102-2220-E-150-001. The authors thank the National Chip Implementation Center (CIC) of Taiwan for technical support.

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  1. Department of Electrical Engineering, National Formosa University, No. 64, Wunhua Rd., Huwei Township, Yunlin County, 632, Taiwan

    Kuang-Hao Lin & Meng-Yi Lin

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  1. Kuang-Hao Lin
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  2. Meng-Yi Lin
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Correspondence to Kuang-Hao Lin.

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Lin, KH., Lin, MY. High-Throughput Architectures for Circular Block-Type Low-Density Parity-Check Codes. Circuits Syst Signal Process 34, 2993–3009 (2015). https://doi.org/10.1007/s00034-015-9993-8

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  • DOI: https://doi.org/10.1007/s00034-015-9993-8

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