Abstract
Implementation of Low Density Parity Check (LDPC) decoders using conventional algorithms such as LLR BP or Min-Sum requires large amount of memory resources for storing the parity check matrix. This paper presents a soft implementation of irregular LDPC decoding for Wimax application, which achieve better BER performance and faster convergence with less memory requirement. The proposed construction reduce the memory required for loading the LDPC parity-check matrix by up to 98%, and subsequently reduce the decoding latency to 0.7 ms by iteration.
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Benhayoun, M., Razi, M., Mansouri, A., Ahaitouf, A. (2021). Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder. In: Hajji, B., Mellit, A., Marco Tina, G., Rabhi, A., Launay, J., Naimi, S. (eds) Proceedings of the 2nd International Conference on Electronic Engineering and Renewable Energy Systems. ICEERE 2020. Lecture Notes in Electrical Engineering, vol 681. Springer, Singapore. https://doi.org/10.1007/978-981-15-6259-4_5
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DOI: https://doi.org/10.1007/978-981-15-6259-4_5
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