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Efficient Implementations for AES Encryption and Decryption

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Abstract

This paper proposes two efficient architectures for hardware implementation of the Advanced Encryption Standard (AES) algorithm. The composite field arithmetic for implementing SubBytes (S-box) and InvSubBytes (Inverse S-box) transformations investigated by several authors is used as the basis for deriving the proposed architectures. The first architecture for encryption is based on optimized S-box followed by bit-wise implementation of MixColumns and AddRoundKey and optimized Inverse S-box followed by bit-wise implementation of InvMixColumns and AddMixRoundKey for decryption. The proposed S-box and Inverse S-box used in this architecture are designed as a cascade of three blocks. In the second proposed architecture, the block III of the proposed S-box is combined with the MixColumns and AddRoundKey transformations forming an integrated unit for encryption. An integrated unit for decryption combining the block III of the proposed InvSubBytes with InvMixColumns and AddMixRoundKey is formed on similar lines. The delays of the proposed architectures for VLSI implementation are found to be the shortest compared to the state-of-the-art implementations of AES operating in non-feedback mode. Iterative and fully unrolled sub-pipelined designs including key schedule are implemented using FPGA and ASIC. The proposed designs are efficient in terms of Kgates/Giga-bits per second ratio compared with few recent state-of-the-art ASIC (0.18-μm CMOS standard cell) based designs and throughput per area (TPA) for FPGA implementations.

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Notes

  1. The SubBytes and InvSubBytes implementation described here has been presented in TENCON 2009 [18].

References

  1. Advanced encryption standard (AES), Federal Information Processing Standards Publications FIPS 197. http://csrc.nist.gov/publication/fips-197.pdf, November 2001

  2. P. Chodowiec, K. Gaj, P. Bellows, B. Schott, Experimental testing of the gigabit IPSec-compliant implementations of Rijndael and triple DES using SLAAC-1V FPGA accelerator board, in Proc. Information Security Conference, Malaga (2001), pp. 220–234

    Google Scholar 

  3. M. Fayed, M. El-Kharashi, F. Watheq Gebali, A high-speed, fully-pipelined VLSI architecture for real-time AES, in 4th International Conference on Information & Communications Technology (2006)

    Google Scholar 

  4. K. Gaj, P. Chodowiec, Very compact FPGA implementation of AES algorithm, in Cryptographic hardware and Embedded Systems—CHES 2003, 5th International Workshop, Germany. Lecture Notes in Computer Science, vol. 2779 (2003), pp. 319–333

    Chapter  Google Scholar 

  5. T. Good, M. Benaissa, Very small FPGA application specific instruction processor AES. IEEE Trans. Circuits Syst. 53(7), 1477–1486 (2006)

    Article  Google Scholar 

  6. T. Good, M. Benaissa, Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment). IET Proc. Inf. Secur. 1, 1–10 (2007)

    Article  Google Scholar 

  7. I. Hammad, K. Sankary, E. El-Masry, High-speed AES encryptor with efficient merging techniques. IEEE Embed. Syst. Lett. 2(3), 67–71 (2010)

    Article  Google Scholar 

  8. A. Hodjat, I. Verbauwhede, A 21.54 Gbps fully pipelined AES coprocessor on FPGA, in 12th Annual Symposium on Field-Programmable Custom Computing Machines, FCCM 2004 (2004), pp. 308–309

    Chapter  Google Scholar 

  9. A. Hodjat, I. Verbauwhede, Area-throughput trade-offs for fully pipe-lined 30 to 70 Gbits/s AES processors. IEEE Trans. Comput. 55, 366–372 (2006)

    Article  Google Scholar 

  10. S.F. Hsiao, M.C. Chen, C.S. Tu, Memory-free low cost design of advanced encryption standard using common subexpression elimination for subfunctions in transformations. IEEE Trans. Circuits Syst. I, Regul. Pap. 5(3), 615–626 (2006)

    Article  Google Scholar 

  11. Y.S. Jeon, Y.J. Kim, D.H. Lee, A compact memory-free architecture for the AES algorithm using resource sharing methods. J. Circuits Syst. Comput. 19, 1109–1130 (2010)

    Article  Google Scholar 

  12. H. Kuo, I. Verbauhede, P. Schaumont, A 2.29 Gb/s, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 μm CMOS technology, in Proc. IEEE Custom Integrated Circuit Conference (2002), pp. 147–150

    Google Scholar 

  13. R. Liu, K.K. Parhi, Fast composite field S-box architectures for advanced encryption standard, in GLSVLSI’08: Proceedings of the 18th ACM Great Lakes Symposium on VLSI (ACM, New York, 2008), pp. 65–70

    Chapter  Google Scholar 

  14. M. McLoone, J.V. McCanny, Rijndael FPGA implementation utilizing look-up tables. J. VLSI Signal Process. 34, 261–275 (2003)

    Article  MATH  Google Scholar 

  15. S. Morioka, A. Satoh, A 10 Gbps Full-AES crypto design with a twisted-BDD S-box architecture, in Proc. IEEE International Conference on Computer Design, Freiburg, Germany (2002), pp. 98–103

    Google Scholar 

  16. E.N.C. Mui, Practical implementation of Rijndael S-box using Combinational logic. www.xess.com/projects/Rijndael_Sbox.pdf. Cached page

  17. R.R. Rachh, P.V.A. Mohan, Implementation of AES S-boxes using combinational logic, in Proc. IEEE International Symposium on Circuits and Systems, Seattle, Washington (2008), pp. 3294–3297

    Google Scholar 

  18. R.R. Rachh, P.V.A. Mohan, B.S. Anami, Efficient implementations of AES S-box and inverse S-box, in Proc. IEEE TENCON, Singapore (2009), pp. 1–6

    Google Scholar 

  19. G. Rouvroy, F. Standaert, J. Legat, J.-J. Quisquater, Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications, in Proc. of the International Conference on Information Technology: Coding and Computing (2004), pp. 583–587

    Chapter  Google Scholar 

  20. A. Rudra, J.R. Rao, P. Rohatgi, Efficient implementation of Rijndael encryption with composite field arithmetic, in Proc. Cryptographic Hardware Embedded Systems, Paris, France (2001), pp. 171–184

    Google Scholar 

  21. A. Satoh, S. Morioka, K. Takano, A compact Rijndael hardware architecture with S box optimization, in ASIACRYPT 2001. Lecture Notes in Computer Science, vol. 2248 (2001), pp. 239–254

    Chapter  Google Scholar 

  22. T. Vinh, J. Park, Y. Kim, K. Kim, An FPGA implementation of 30 Gbps security module for GPON systems, in Proc. IEEE Conference on Computer and Information Technology (2008), pp. 868–872

    Google Scholar 

  23. M.Y. Wang, C.P. Su, C.L. Horng, C.W. Wu, C.T. Huang, Single- and multi-core configurable AES architectures for flexible security. IEEE Trans. VLSI Syst. 18, 541–552 (2010)

    Article  Google Scholar 

  24. J. Wolkerstorfer, E. Oswald, M. Lamberger, An ASIC implementation of the AES S-boxes, in Proc. Cryptographer’s Track at the RSA Conference. LNCS, vol. 2271 (Springer, Berlin, 2002), pp. 67–78

    Google Scholar 

  25. M.M. Wong, M.L.D. Wong, A high throughput low power compact AES S-box implementation using composite field arithmetic and algebraic normal representation, in Proc. IEEE 2nd Asia Symposium on Quality Electronic Design (2010), pp. 318–323

    Chapter  Google Scholar 

  26. J. Zambreno, D. Nguyen, A. Choudhary, Exploring area/delay trade-offs in an AES FPGA implementation, in Proc. International Conference on Field Programmable Logic and Applications, Antwerp, Belgium. Lecture Notes in Computer Science, vol. 3203 (2004), pp. 575–585

    Google Scholar 

  27. X. Zhang, K.K. Parhi, Implementation approaches for the AES algorithm. IEEE Circuits Syst. Mag. 2(4), 1477–1486 (2002)

    Google Scholar 

  28. X. Zhang, K.K. Parhi, High speed VLSI architectures for AES algorithm. IEEE Trans. VLSI Syst. 12(9), 957–967 (2004)

    Article  Google Scholar 

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Acknowledgement

The authors wish to thank the anonymous reviewers for their useful comments which have enhanced the value of the paper.

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Authors and Affiliations

  1. Department of Computer Science, KLE Society’s College of Engineering and Technology, Belgaum, 590008, India

    Rashmi Ramesh Rachh

  2. R&D, ECIL, 30/1 Cunningham Road, Bangalore, 560052, India

    P. V. Ananda Mohan

  3. K.L.E. Institute of Technology, Hubli, India

    B. S. Anami

Authors
  1. Rashmi Ramesh Rachh
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  2. P. V. Ananda Mohan
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  3. B. S. Anami
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Corresponding author

Correspondence to P. V. Ananda Mohan.

Appendix

Appendix

The expression for \(s'_{37}\) of the output of integrated unit for encryption is given as

(A.1)

The expression for \(r'_{37}\) of the output of integrated unit for decryption is given as

(A.2)

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Rachh, R.R., Mohan, P.V.A. & Anami, B.S. Efficient Implementations for AES Encryption and Decryption. Circuits Syst Signal Process 31, 1765–1785 (2012). https://doi.org/10.1007/s00034-012-9395-0

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