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An effective test generation algorithm for combinational circuits

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Abstract

In this paper, an analysis of backtrack behavior in PODEM (the test generation algorithm for combinational circuits presented by P. Goel) is given. It is pointed out that there are still many unnecessary backtracks in PODEM on some occasions. A new test generation algorithm named IPODEM is therefore proposed in this paper. IPODEM is an improvement over PODEM with emphasis on backtrack of decision tree. A new backtrack approach is developed in this algorithm. It is shown that onlyO(j) of backtrack consumption is needed in IPODEM compared withO(2j) in PODEM on certain occasions. Experiments pointed out that these occasions appear in not small proportion. Several other techniques are applied in IPODEM to accelerate test generation process in other aspects. Experimental results demonstrated that IPODEM is faster than PODEM for both hard-testing and easy-testing single stuck fault, and that the former has higher test coverage than the latter.

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References

  1. J.P. Roth, Diagnosis of automata failures: A calculus and a method.IBM J. Res. Develop., 10(1966), 278–291.

    Article  MATH  MathSciNet  Google Scholar 

  2. F.F. Sellers, M.Y. Hsiao and L.W. Bearnson, Analyzing errors with the Boolean difference,IEEE Trans. Comput., C-17:7(1968), 676–683.

    Article  MATH  Google Scholar 

  3. C.W. Cha, W.E. Donath and F. Ozguner, 9-V algorithm for test pattern generation of combinational digital circuits,IEEE Trans. Comput., C-27:3(1978), 193–200.

    Article  Google Scholar 

  4. Wei Daozheng, The test generation for large combinational circuits.Chinese Journal of Computers,1:2 (1978), 93–98.

    Google Scholar 

  5. P. Goel, An implicit enumeration algorithm to generate tests for combinational logic circuits,IEEE Trans. Comput., C-30:3(1981), 215–222.

    Article  MATH  MathSciNet  Google Scholar 

  6. H. Fujiwara and T. Shimono, On the acceleration of test generation algorithms, Proc. 13th Int. Symp. on Fault Tolerant Computing, 93–105, 1983.

  7. O.H. Ibarra and S. Sahni, Polynomially complete fault detection problems,IEEE Trans. Comput., C-24:3(1975), 242–249.

    Article  MATH  MathSciNet  Google Scholar 

  8. E.B. Eichelberger and T.W. Williams, A logic design structure for LSI testing, Proc. of the 14th Design Automation Conf., 462–468, 1977.

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Authors and Affiliations

  1. Institute of Computing Technology, Academia Sinica, Beijing, China

    Wang Jianchao & Wei Daozheng

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  1. Wang Jianchao
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  2. Wei Daozheng
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Wang, J., Wei, D. An effective test generation algorithm for combinational circuits. J. of Compt. Sci. & Technol. 1, 1–16 (1986). https://doi.org/10.1007/BF02943304

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  • DOI: https://doi.org/10.1007/BF02943304

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