Abstract
The numerical simulation of two dimensional device is conducted to describe the mechanism of the special substrate current and degradation of submicron LDD structure observed in experiments, and finally, the optimum processes for submicron LDD CMOS are proposed.
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References
S. Ogura, P. J. Tsang, W. W. Walker et al.,IEEE Trans. on ED,ED-27 (1980) 8, 1359–1367.
J. Hui, F-C. Hsu, J. Moll,IEEE Electron Device Lett. 6 (1985) 3, 135–138.
F-C. Hsu, K. Y. Chiu,IEEE Electron Device Lett. 5 (1984) 5, 162–165.
Du Ming, Huang Chang,Chinese Journal of Semiconductors,9 (1988) 1, 1–6 (in Chinese).
P. N. Andhare, R. K. Nahar, N. M. Devashrayee et al.,Microelectronics Reliab.,30 (1990) 4, 681–690.
M. Koyanagi, A. G. Lewis, R. A. Martin et al.,IEEE Trans. on ED,ED-34 (1987) 4, 839–844.
Yu Shan, Zhang Dingkang, Huang Chang,Chinese Journal of Semiconductors,13 (1992) 7, 423–429 (in Chinese).
Yu Shan, Zhang Dingkang, Huang Chang, “Development of 0.50μm CMOS Integrated Circuits Technology”, Proc. of 3rd ICSICT. Beijing: 1992, 143–146.
Yu Shan, Zhang Dingkang, Huang Chang, “1μm High Speed LDD CMOS Titanium Silicide Bus Exchange Logic Integrated Circuit”, Proc. of The First National Conference on Applications in Special Integrated Circuits(ASIC) of China. Wuxi: 1990, 203–204 (in Chinese).
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Shan, Y., Dingkang, Z. & Chang, H. 0.8μm LDD CMOS reliability experiments and analysis. J. of Electron. (China) 12, 84–89 (1995). https://doi.org/10.1007/BF02684572
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DOI: https://doi.org/10.1007/BF02684572