Abstract
3D wafer-level chip scale packaging (3D WLCSP) using via last through silicon via (TSV) technology is an ideal technology to meet small-form-factor, high I/O density, high-speed, short time to market and lower cost product requirements. In this study, process development and reliability evaluation of 3D WLCSP for CMOS Image Sensor (CIS) using vertical TSVs with 3:1 aspect ratio were presented. Key processes including wafer bonding, wafer backside grinding, silicon etch, bottom oxide etch, via cleaning, barrier/seed layer deposition, electroplating, redistribution layer (RDL) and ball grid array (BGA) formation were developed. Reliability of the developed WLCSP was characterized by various tests. The failed devices after reliability tests were analyzed using microstructure observation and finite element simulation for stress distribution of TSV structure. The results indicate that WLCSP with vertical via last scheme can provide a reliable, low-cost solution for the next-generation CIS requiring high density routing.
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This research is supported by National Science and Technology Major Project No. 2014ZX02502.
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Xiao, Z., Yao, M., Yu, D. et al. Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio. Microsyst Technol 23, 4879–4889 (2017). https://doi.org/10.1007/s00542-016-3267-7
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DOI: https://doi.org/10.1007/s00542-016-3267-7