Abstract
Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach.
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Goossens, G., Lanneer, D., Pauwels, M. et al. Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures. Journal of VLSI Signal Processing 9, 49–65 (1995). https://doi.org/10.1007/BF02406470
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DOI: https://doi.org/10.1007/BF02406470