Efficient board interconnect testing using the split boundary scan register

Abstract

This article presents a new approach to testing board interconnects, on a board containing chips equipped with the Boundary Scan Architecture. The proposed technique reduces the test time, test vector size, and requires an order independent test set at the expense of minimal hardware overhead to the ANSI/IEEE Std. 1149.1-1990 standard. Although most of the algorithms developed so far can be used to test boards under this scheme, we have concentrated on the Walking 1's and 0's for the purpose of presenting this technique. This test can be applied with a reduced time complexity for test generation and application. Furthermore, with local response compaction this scheme can easily be used for BIST implementation, resulting in the application of Walking 1/0 in linear time. All of the above results assume boards that contain 3-state nets, which is an improvement over previously reported results.