Abstract
The design of a test access port controller conforming to the boundary scan standard is described, which is implicitly tested while it is working. It is based on a novel self-test technique also applicable to other controller designs. This technique uses a signature register as state register, such that no reconfiguration of that register is necessary during self-test. This way the test of the test access port can be efficiently incorporated into the system self-test. No additional I/O pins beyond those of the boundary scan standard are necessary, neither does the test program have to be changed to incorporate the test of the controller. The solution only requires moderate hardware overheads, nevertheless it guarantees a high fault coverage.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
IEEE Std. P1149.1: Standard Test Access Port and BoundaryScan Architecture, 1990.
A. Dahbura, M. Uyar and C. Yau, “An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller,” Proc. Int. Test Conference, pp. 55–62, 1989.
B. Könemann, J. Mucha and G. Zwiehoff, “Built-in logic block observation techniques,” Proc. Int. Test Conference, pp. 37–41, 1979.
C. Chuang and A. Gupta, “The analysis of parallel BIST by the combined markov chain (CMC) model,” Proc. Int. Test Conference, pp. 337–343, 1989.
L. Wang and E. McCluskey, “Built-in self-test for sequential machines,” Proc. Int. Test Conference, pp. 334–341, 1987.
K. Kim, D. Ha and J. Tront, “On using signature registers as pseudorandom pattern generators in built-in self-testing,” IEEE Transactions on CAD, vol. 8. pp. 919–928, 1988.
A. Krasniewski and S. Pilarski, “Circular self-test path: A lowcost BIST technique for VLSI circuits,” IEEE Transactions on CAD, vol. 8, pp. 46–55, January 1989.
B. Eschermann and H.J. Wunderlich, “A unified approach for the synthesis of self-testable finite state machines,” Proc. 28th Design Automation Conference, pp. 372–377, 1991.
B. Eschermann, “Test-friendly synthesis of VLSI controllers,” (in German), PhD Dissertation, Dept. of Computer Science, U. of Karlsruhe, May 1991, to be published by Springer, Berlin, 1992.
T. Booth, Sequential Machines and Automata Theory, New York: John Wiley, 1967.
W. Feller, An Introduction to Probability Theory and its Applications; New York: John Wiley, 1957.
S. Devadas, H.K.T. Ma, A.R. Newton, and A. Sangiovanni-Vincentelli, “Irredundant sequential machines via optimal logic synthesis,” IEEE Transactions on Computer-Aided Design, vol. CAD-9, pp. 8–18, January 1990.
F. J. Fritz, B. Huppert, W. Willems, Stochastische Matrizen; Berlin: Springer, 1979.
H.J. Wunderlich, “Multiple distributions for biased test patterns,” IEEE Transactions on CAD, vol. 9, pp. 584–593, June 1990.
GenRad Ltd., System HILO System Reference Manual, 1988.
Octtools Distribution 4.0, University of California, Berkeley, 1990.
T. Williams and W. Daehn, “Aliasing probability for multiple input signature analyzers with dependent inputs,” Proc. 3rd CompEuro, pp. 120-5.127, 1989.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Eschermann, B. An implicitly testable boundary scan TAP controller. J Electron Test 3, 159–169 (1992). https://doi.org/10.1007/BF00137253
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00137253