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An Interpolator for Signal Peak Detection in Front-end Electronics

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Abstract

The interpolator is designed to determine the maximum signal amplitude in the analog channel of a readout ASIC. The use of an interpolator allows to mitigate the requirements for the sampling frequency of an analog-to-digital converter built into the channel of the readout ASIC. Design process and test results of an interpolator unit implemented by means of a FPGA are described.

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Authors and Affiliations

  1. National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), 115409, Moscow, Russia

    V. V. Shumikhin, D. A. Azarov, E. V. Atkin, I. S. Bulbakov, P. Yu. Ivanov & D. D. Normanov

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  1. V. V. Shumikhin
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  2. D. A. Azarov
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  3. E. V. Atkin
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  4. I. S. Bulbakov
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  5. P. Yu. Ivanov
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  6. D. D. Normanov
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Corresponding author

Correspondence to V. V. Shumikhin.

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This work was supported by Russian Science Foundation (grant no. 18-79-10259).

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Shumikhin, V.V., Azarov, D.A., Atkin, E.V. et al. An Interpolator for Signal Peak Detection in Front-end Electronics. Instrum Exp Tech 63, 41–45 (2020). https://doi.org/10.1134/S0020441220010169

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  • DOI: https://doi.org/10.1134/S0020441220010169

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