Introduction

Scalability is one of the most important concerns in complementary metal–oxide–semiconductor (CMOS) device and circuit design1. Over the past several decades, the metal–oxide–semiconductor field-effect transistor (MOSFET) has been continuously scaled down to achieve higher performance and higher packing density with lower cost. An undesirable consequence of this aggressive down-scaling has been the appearance of adverse short-channel effects (SCEs), as well as increasingly challenging fabrication limits. To mitigate the SCEs, and continue further down-scaling, innovative device structures such as FinFETs, gate-all-around (GAA) FETs and a nanosheet (NS) based FET, have been introduced2,3,4,5,6. These new device structures have been able to suppress the off-state current (Ioff), which is fatal to the power consumption of a chip in the stand-by state. However, even with the above structural innovations, there are still limits that require device and process parameters to be continuously optimized.

Another approach to improving on-state current (Ion) and chip performance has focused on the use of new materials, such as strained Si/SiGe and III–V compound semiconductors7,8,9. Although the new materials have advantages, silicon is still the most attractive material when CMOS-compatibility with low-cost is considered10.

In the meanwhile, multi-valued logic (MVL) has also been considered promising architecture to overcome the MOSFET scaling limitations from a circuit point of views. The MVL system can reduce the burden of circuit complexity inherent to binary-based logic circuits, by converting a multiple-output Boolean function into a single-output multiple-valued function11,12. In one particular case, a ternary-based logic circuit reduced the total cost and power consumption by minimizing the number of required inputs, resulting in the simplification of metal interconnection, compared to other MVL systems13.

In spite of these potential advantages, the practicality of ternary logic design heavily relies on the availability of the device and circuitry, which must be compatible with present-day binary CMOS technologies12. Binary operation has been the mainstay of modern computing system. To take full advantage of ternary logic, a mixed radix system (MRS) using both ternary and binary logic would be more suitable, rather than exclusively using ternary logic. To implement a MRS, conversion from a ternary code to a binary code is essential and vice versa14,15,16. This requires a ternary logic decoder (TLD). Logic blocks such as a ternary logic multiplexer (TLM), a TLM-based half adder and comparator can be implemented based on the TLD17.

To realize a TLD, a logic scheme for multi-threshold voltage (multi-Vth) is necessary18. There have been two approaches used to implement a multi-Vth scheme. One uses physical methods, by tuning the work-function of a metal gate19 and by modulating the channel or body doping concentration by ion implantation20. The other utilizes electrical methods, applying back bias to a body in the MOSFET or potential redistribution in a gate electrode21. However, the aforementioned methods have several challenging issues. The gate work-function engineering increases process complexity, and limits the spectrum of potential materials, which can lead to a work function variation (WFV) problem given the variability in grain size22. Adjustment of Vth by ion implantation also involves issues with complementary dopants, accurate depth and concentration control, diffusivity, implantation-induced damages, and random dopant fluctuations. Moreover, channel doping concentration has little effect on Vth control for a thin gate dielectric and a fully-depleted thin-body channel23,24,25.

With the electrical approach, additional static back bias in the bulk planar MOSFET increases parasitic capacitance and leakage, which can degrade device performances. In any case, fine tuning the Vth is not an easy task, because Vth modulated by applied static back bias does not follow a linear relationship. In addition, the static back bias can degrade Ioff and subthreshold swing (SS). For the gate electrode potential redistribution method, another challenging issue has been observed, an increase in static power consumption21.

In another approach, a previous study attempted to control Vth dynamically by using the four-terminals of an independently controlled double-gate (ICDG) FinFET26─31. Such a novel device could mitigate the abovementioned problems by allowing multi-Vth. But, there have been no reports of using ICDG devices for TLD so far. A primary goal of the present work is to demonstrate a TLD composed of ICDG silicon-nanowire (Si-NW) MOSFETs, and to confirm the feasibility of manufacturing a MRS chip. Because of their inherent CMOS-compatibility and simplicity, the proposed TLD would be a promising option for realizing a mixed radix circuit.

Results and discussion

Supplementary Fig. S1 shows a simplified sequence of the experimental details. N-channel ICDG Si-NW MOSFETs were fabricated, modeled, and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator32. Thereafter, a P-channel ICDG Si-NW MOSFET was regenerated as a counter-part of the N-channel by simulations. Following device-level simulations, further analyses of the TLD circuit performance and power consumption were conducted using ATLAS mixed-mode TCAD simulations to predict the TLD behaviors at an elementary circuit level, as an extension. All of the abbreviations and nomenclature of variables are summarized in Supplementary Table S1.

Fabrication process of the ICDG Si-NW MOSFET is summarized in Supplementary Fig. S2. Figure 1 shows a schematic of the ICDG Si-NW MOSFET and scanning electron microscopy (SEM) and transmission electron microscopy (TEM), images of the fabricated ICDG Si-NW MOSFET. The fabricated ICDG Si-NW MOSFET was composed of two gates, a drive gate and a control gate, positioned at each sidewall of the Si-NW to control the current flowing in the Si-NW. The drive gate turns the channel on or off. The control gate modulates threshold voltage as a body electrode does in a conventional bulk-MOSFET. The fabricated device had a Si-NW width (WSi) of 70 nm, a gate length (LG) of 500 nm, a Si-NW height (HSi) of 50 nm and a gate dielectric thickness (Tox) of 10 nm. The dimensions of the modeled device were the same as the fabricated device. Source, body, and drain doping concentration were set to 1 \(\times\) 1020 cm–3, 1 \(\times\) 1015 cm–3, 1 \(\times\) 1020 cm–3, respectively. Various models such as Schockly-Read-Hall (SRH), bandgap narrowing (BGN), Fermi–Dirac (FERMI), energy balance model (EBM), non-local band-to-band tunneling (BTBT), trap-assisted tunneling (TAT), and quantum effect (QUANTUM for electrons and P.QUANTUM for holes) were utilized for the simulations. The P-channel ICDG Si-NW MOSFET was modeled in the same manner as the N-channel device, except for the doping polarity and HSi. The dopant of the P-channel device was the opposite that of the N-channel device, and the HSi was doubled considering the difference in carrier mobility of electrons and holes.

Figure 1
figure 1

Overall structure of the ICDG Si-NW MOSFET. (a) Cross-sectional schematic of the ICDG Si-NW MOSFET along with the channel direction. (b) Cross-sectional schematic of the ICDG Si-NW MOSFET along with the gate direction. (c) SEM image of the fabricated ICDG Si-NW MOSFET. (d) Cross-sectional TEM image of the fabricated ICDG Si-NW MOSFET along with the gate direction.

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Figure 2(a) and (b) show the ID-VdGS characteristics of the measured and simulated N-channel ICDG Si-NW MOSFET, respectively. The ID–VdGS curves are shown for various |VcGS|. Measured and simulated ID–VDS characteristics of N-channel ICDG Si-NW MOSFET are superimposed for VcGS =  0.4 V (Fig. 2c) and VcGS = − 1.5 V (Fig. 2d) on the log-scaled y-axis and linear-scaled y-axis. They (measured and simulated) are very similar to each other. Because individual gate addressing is possible thanks to the use of two local gates, the channel potential of the Si-NW can be controlled independently33. One of the two gates is used to sweep the gate voltage of the drive gate while a constant voltage is applied to the other gate, which is the control gate to precisely tune the channel potential of the Si-NW. A shift in Vth and its multiple values by VcGS are shown in Fig. 2e. The Vth shift by VcGS has linear relationship. The results are consistent with the previously reported data26,27,28,29,30,31. As the |VcGS| increased, the ID-VdGS curve shifted rightward in parallel and the Vth was increased. Herein, leakage current is defined as off-state current at VdGS of 0 V. The measured leakage current from the fabricated ICDG Si-NW NMOSFET was decreased from 10 pA to 300 fA as the |VcGS| was increased from 0.4 V to 1.5 V. Figure 2f shows the symmetrically overlaid ID-VdGS curves of the simulated N-channel and P-channel ICDG Si-NW MOSFET. Here, there is a wide overlapped region between the N-channel device and the P-channel device. This wide overlapped region stably creates a intermidiate output signal (output ‘1’), which enables the TLD. It becomes wider as the applied |VcGS| increases.

Figure 2
figure 2

(a) Measured ID-VdGS characteristics from the fabricated ICDG NMOS for various |VcGS|. (b) Semi-empirically simulated ID-VdGS characteristics according to various |VcGS|. Superimposition of measured and simulated ID-VDS characteristics of N-channel for (c) |VcGS|= 0.4 V and (d) 1.5 V on the log-scaled y-axis and linear-scaled y-axis. (e) Linear Vth shift by VcGS. (f) Simulated ID-VdGS characteristics of both ICDG NMOS and PMOS for various |VcGS|.

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Note that there are negative ternary inverters (NTI) and positive ternary inverters (PTI) in ternary logic. Its output state becomes ‘0’ or ‘2’ when the input state is ‘1′18 as shown in Fig. 3b. The proposed TLD was composed of NTI, PTI, and negative ternary NOR (NTNOR)18. To implement the TLD, the characteristics of NTI and PTI should be confirmed.

Figure 3
figure 3

(a) Complementary inverter circuits composed of ICDG NMOS and PMOS with each control gate. They can serve as the NTI and the PTI by adjusting VcGN and VcGP. (b) Truth table of the NTI and PTI. (c) Input–output voltage transfer curves (VTCs) of the inverter circuit for various |VcGNS| and |VcGPS|. (d) Current (IVDD) from the VDD node to the ground node versus input voltage (Vin) and power consumption (PVDD) versus input voltage (Vin).

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As shown in Fig. 3a, the ternary inverter circuitry is similar to a typical binary inverter except for the use of the control gates. The complementary circuit shown in Fig. 3a can become both the NTI and the PTI by adjusting VcGN and VcGP. As shown in Fig. 3c, the voltage transfer curve (VTC) is shifted in parallel as |VcGNS| increases from 0.4 V to 2.1 V and |VcGPS| decreases from 2.0 V to 0.3 V. For the NTI, an input voltage (Vin) of 0.5 V (state ‘1’) is transformed to a Vout of 0 V (state ‘0’) because |Vth| in the P-channel device is higher than that of the N-channel device. In contrast, the Vin of 0.5 V (state ‘1’) is converted to a Vout of 1 V (state ‘2’) in the case of the PTI, due to the higher |Vth| of the N-channel device.

Figure 3d shows the IVDD and PVDD characteristics versus the Vin. The IVDD increased and decreased exponentially as the N-channel and P-channel devices started to turn on and turn off, respectively, at a certain voltage. Peak points of the IVDD curve at a certain voltage, were shifted as the |VcGNS| and |VcGPS| changed. PVDD can be obtained by multiplying the IVDD by VDD for various Vin, as shown in the 2nd y-axis in Fig. 3d. We can average PVDD for three states with a different weighting factor: w0 for state ‘0’, w1 for state ‘1’ and w2 for state ‘2’. This is represented by < PVDD > avg = (w0⋅PVDD|state=0 + w1⋅PVDD|state=1 + w2⋅PVDD|state=2)/(w0 + w1 + w2). This averaged PVDD is approximated to (1/3)⋅w1⋅PVDD|state=1 under the condition of w0 = w1 = w2, because the PVDD|state=2 and PVDD|state=0 are much smaller than the PVDD|state=1. It should be noted that IVDD for state ‘1’ is much larger than that at the state ‘0’ and ‘2’. When the curve (green line) of a typical binary inverter in Fig. 3d is shifted to the NTI or the PTI, the PVDD|state=1 decreases. Accordingly, the total PVDD decreases.

A 1-to-3 TLD circuit was designed to examine the feasibility of the ICDG Si-NW MOSFET for the TLD. The TLD consisted of 10 complementary ICDG Si-NW MOSFETs. Figure 4a shows the TLD logic circuit and its VTCs for an output ‘0’, output ‘1’, and output ‘2’ versus the Vin. The NTNOR CMOS circuitry was the same as the typical binary NOR except for the use of the control gates. The device models for the NTNOR were identical to the device models described in Fig. 2. As shown in the VTC graph in Fig. 4a, the TLD stably accepts voltage near 0.5 V as an input then it produces the third output voltage (output ‘1’). The behaviors of the TLD were verified using the ATLAS mixed-mode TCAD simulations, as shown in Fig. 4b and c. Voltage levels of 1 V (VDD), 0.5 V (half VDD), and 0 V (VSS) are equivalent to a logic value of ‘2’, ‘1’, and ‘0’, respectively. Figure 4d shows a diagram of the state transition with propagation delay time. Note that the transition time is related to on-current of a MOSFET. According to the result of Fig. 4d, t2 (‘1’ → ‘0’) was almost the same as t5 (‘2’ → ‘0’) because both the t2 and t5 depend on the on-current of an n-channel pull-down transistor (Ion, ‘0’). Likewise, t3 (‘1’ → ‘2’) was the same as t6 (‘0’ → ‘2’) because both the t3 and t6 depend on the on-current of a p-channel pull-up transistor (Ion, ‘2’). t1 and t4 are dominated by on-current (Ion, ‘1’) at an intermediate state. Ion, ‘1’ is defined as the drain current at VdGS = VDD/2. As shown in Fig. 2f, the Ion, ‘1’ was smaller than the Ion, ‘0’ and Ion, ‘2’. Therefore, t1 and t4 were longer than the other transition times (t2, t3, t5, and t6). Additionally, the difference between t1 and t4 was arisen from a slight disparity of ID between Ion, ‘1’ of a p-channel MOSFET and an n-channel MOSFET. The delay time (τd) is dominated by the longest transition time (t1). To reduce the delay time, Ion, ‘1’ modulated by |VcGS| should be maximized as large as possible.

Figure 4
figure 4

(a) 1-to-3 ternary logic decoder circuit composed of NTI, PTI and NTNOR and the VTCs of output ‘0’, output ‘1’ and output ‘2’. (b) Transient ternary responses of output ‘0’, output ‘1’, output ‘2’ versus time (fin = 12.5 MHz). (c) Transient binary responses for direct alteration between states ‘2’ and ‘0’. (d) Diagram of state transition with propagation delay time.

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Based on SILVACO ATLAS TCAD simulator, the scaling analysis was implemented by reducing device dimensions (LG, WSi, HSi, and Tox). The detailed information of those is shown in Supplementary Table S2. Figure 5 shows a quantitative analysis of gate capacitance (Cgg) and Ion, ‘1’. Figures 5a and b show the Cgg-VdG characteristics depending on LG under certain VcG conditions which were optimized for Vth-modulation. Optimization of Vth-modulation according to VcG can be performed with consideration of two conflicting demands: maximization of speed and minimization of static power consumption. Increment of Ion, ‘1’ through the VcG modulation can result in boosting speed of the ternary logic decoder (TLD). But, excessive increment of Ion, ‘1’ can adversely increase the static power consumption (P) of the TLD owing to a parallel shift of Vth, which provokes increment of leakage current. Thus, the optimization of VcG can be done with a well-known figure of merit, power-delay product (PDP) owing to the abovementioned trade-off relationship. The magnitude of Cgg for N-channel and P-channel ICDG Si-NW MOSFETs was decreased as LG was decreased. As shown in Fig. 4c and d, as LG was decreased, Cgg was continuously decreased, while Ion, ‘1’ was maintained by Vth-modulation. It means that delay time (τd) of the TLD circuit is decreased by down-scaling.

Figure 5
figure 5

The Cgg-VdG characteristics of ICDG (a) NMOS and (b) PMOS depending on gate length (LG) reduction. Ion, ‘1’ and Cgg of ICDG (c) NMOS and (d) PMOS according to gate length reduction.

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Figure 6a and b show two transient current responses for an LG of 500 nm and an LG of 14 nm, respectively at input voltage frequency (fin) of 12.5 MHz. The fin of 12.5 MHz was used from T = 1/fin = 80 ns as shown in Fig. 4b first graph. When the input voltage signal abruptly switched from one state to another, charges were transferred from the power supply to the gate capacitors or load capacitors. And |IVDD| rapidly increased and temporarily overshot, thereafter it began to stabilize. As shown in Fig. 6b, the pulse width needed to induce the overshoot was significantly reduced by down-scaling from LG = 500 nm to LG = 14 nm. The stabilized |IVDD| depended on the applied Vin (state of input). The magnitude of the stabilized |IVDD| for the input voltage of 0.5 V (state ‘1’) was much higher than that for the other states, like the |IVDD| of the NTI and PTI shown in Fig. 3d. For an LG = 500 nm, a total PVDD of 6.37 nW was calculated by integrating VDD \(\times\) |IVDD(t)| with respect to the 2 cycle time (2 T = 160 ns) and dividing it by the same time, i.e., \(\left( {{\text{total}}\,{P_{{\text{VDD}}}}} \right)\, = \,[{V_{{\text{DD}}}} \cdot \int_{0\,{\text{ns}}}^{160\,{\text{ns}}} {\left| {{I_{{\text{VDD}}}}(t)} \right|} dt]/(160\,{\text{ns}})\).

Figure 6
figure 6

Transient response of IVDD versus time for (a) LG = 500 nm and (b) LG = 14 nm.

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The TLD was evaluated in terms of τd, P, and PDP. These values were semi-empirically extracted from the simulations, which were based on the fabricated device. Theoretically, τd can be reduced by Vth engineering by biasing the control gate, as well as by device down-scaling. The above three metrics were changed by reducing the gate length (LG), as summarized in Table 1. As shown in Fig. 4d, the propagation delay times, t1 from state ‘0’ to state ‘1’ and t4 from state ‘2’ to state ‘1’ were longer than the other transition times (t2, t3, t5, and t6) because Ion, ‘1’ is smaller than Ion, ‘0’ and Ion, ‘2’. In this work, the τd of TLD is predominantly governed by the longest transition time, t1 (t1 > t4).

Table 1 Power and delay time according to gate length scaling.
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The possible operating frequency was calculated from f = 1 / (4τd)34. Following a constant field scaling scenario with a scaling factor of K (> 1), fin is proportional to K for the down-scaling1. Therefore, the fin for a short LG becomes fin⋅long LG/short LG. For example, an fin of 12.5 MHz for an LG of 500 nm can be increased to 48.1 MHz with an LG of 130 nm. τd was directly extracted and P was extracted for each fin predicted by the abovementioned scaling rule for an LG of 500 nm, 130 nm, 65 nm, 28 nm, and 14 nm, as shown in Table 1. The τd of 5.57 ns for LG of 500 nm was drastically reduced to 0.085 ns for an LG of 14 nm. And the P of 6.37 nW for an LG of 500 nm was also reduced to that of 1.90 nW for LG of 14 nm. In addition, the PDP of 0.16 aJ was extracted from P of 1.9 nW and τd of 0.085 ns for LG of 14 nm. The performance metrics of the proposed TLD are compared with the existing implementations, as shown in benchmarking Table 218,35,36,37,38,39.

Table 2 Benchmarking table of ternary logic decoder.
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The SS of the ICDG Si-NW MOSFET in this experiment was approximately 120 mV/dec, due to the poor interface quality of the TEOS used as the gate oxide. This can be decreased to sub-80 nm/dec replacing the thermally grown oxide or using a high-k dielectric material. Further improvement in the SS will additionally reduce τd and P.

In this study, a ternary logic decoder (TLD) to allow the conversion from a ternary code to a binary code and vice versa has been demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs. Feasibility of the TLD was explored by use of semi-empirical circuit-level simulations based on the measured device-level ICDG Si-NW MOSFET characteristics. Because the ICDG Si-NW MOSFET is not only suitable for a multi-Vth scheme but also CMOS-compatible for mass-production, the proposed TLD would be a promising candidate to realize a MRS. Direct demonstration of the TLD with fully fabricated circuits is left as a further work.

Methods

Electrical measurements

A semiconductor parameter analyzer (B1500A) was used to characterize the fabricated ICDG Si-NW MOSFETs. The transfer characteristics of the fabricated N-channel ICDG Si-NW MOSFET were measured at a constant VDS of 50 mV, whereas the VdGS was swept from 0 to 1 V.

Device modeling

The ICDG Si-NW MOSFETs were modeled and fitted with the SILVACO ATLAS TCAD simulator. A various physical models such as Schockly-Read-Hall (SRH), Bandgap Narrowing (BGN), Fermi–Dirac (FERMI), non-local Band-to-Band Tunneling (BTBT) and Trap-Assisted Tunneling (TAT) were involved.

Circuit simulation for ternary logic decoder

Using the experimentally modeled devices, the operation, performance, and power consumption of the TLD were verified using the ATLAS mixed-mode TCAD simulations. To simulate the transient response of the TLD, VDD and VSS were set to 1 V and 0 V respectively.