Abstract
A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region. Gate oxide and silicon layer form the EG Structure-Oxide-Semiconductor structure that is similar to Metal–Insulator–Semiconductor capacitor. The the N-drift of the EG structure can obtain the charge compensation to overcome the SAD effect, and a nearly rectangular electric field is achieved. In the on-state, the EG structure has two conductive channels and the accumulation layer is formed on the drift region. By accumulating high concentration electrons in the channels, the specific on-resistance (RON,sp) is greatly reduced. When the drift length is 24 μm, 431.4 V breakdown voltage (VB) and 9.8 mΩ cm2 RON,sp are achieved, and the figure of merit is 18.9 MW cm−2.
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M. Amato, V. Rumennik, Comparison of lateral and vertical DMOS specifific on-resistance,” IEDM Tech. Dig. Washington, DC, USA, Dec. 1985, pp. 736–73. 191081 (1985). doi: https://doi.org/10.1109/IEDM
S.G. Nassif-Khalil, C.A.T. Salama, Super-junction LDMOST on a silicon-on-sapphire substrate. IEEE Trans. Electron Devices 50(5), 1385–1391 (2003)
X.-B. Chen, J.K.O. Sin, Optimization of the specifific on-resistance of the COOLMOS. IEEE Trans. Electron Devices 48(2), 344–348 (2001)
B. Zhang, W.T. Zhang, M. Qiao, Z. Li, Theory and optimization of power superjunction devices. China Sci. Mech. Phys. Astron. 46(10), 8–25 (2016)
L. Liang, H. Huang and X. Chen, A variation laterl doping layer and lightly doped region compensated superjunction LDMOS. In: 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, 120–123 (2016)
S. Guo, H. Huang, X.B. Chen, Study of the SOI LDMOS with low conduction loss and less gate charge. IEEE Trans. Electron Devices 65(4), 1645–1649 (2018). https://doi.org/10.1109/TED.2018.2806921
X. Luo et al., Ultralow ON-resistance high-voltage p-channel LDMOS with an accumulation-effect extended gate. IEEE Trans. Electron Devices 63(6), 2614–2619 (2016). https://doi.org/10.1109/TED.2016.2555327
X. Luo et al., Ultralow on-resistance SOI LDMOS with three separated gates and high- k dielectric. IEEE Trans. Electron Devices 63(9), 3804–3807 (2016). https://doi.org/10.1109/TED.2016.2589322
B. Zhang, W. Wang, W. Chen, Z. Li, Z. Li, High-voltage LDMOS With charge-balanced surface low on-resistance path layer. IEEE Electron Device Lett. 30(8), 849–851 (2009). https://doi.org/10.1109/LED.2009.2023541
Hu. Chenming, Optimum doping profile for minimum ohmic resistance and high-breakdown voltage. IEEE Trans. Electron Devices 26(3), 243–244 (1979). https://doi.org/10.1109/T-ED.1979.19416
L. Wu, Q. Ding, Y. Zhang, Y. Huang, L. Zhu, B. Lei, A lateral double-diffusion metal oxide semiconductor device with a gradient charge compensation layer. J. Electron. Mater. (2019). https://doi.org/10.1007/s11664-019-07579-8
L. Wu, Y. Huang, Y. Wu, L. Zhu, B. Lei, Investigation of the stepped split protection gate L-Trench SOI LDMOS with ultra-low specific on-resistance by simulation. Mater. Sci. Semicond. Process. 101, 272–278 (2019). https://doi.org/10.1016/j.mssp.2019.05.035
L. Wu, H. Yang, Y. Zhang, Y. Song, N. Yuan, B. Lei, Y. Wu, A superjunction LDMOS with steps buried oxide. J. Electron. Mater. 47, 6929–6934 (2018)
S. Honarkhah, S. Nassif-Khalil, C. A. T. Salama, Back-etched super-junction LDMOST on SOI. In: Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850), Leuven, Belgium, 117-120 (2004). doi: https://doi.org/10.1109/ESSDER.2004.1356502
B. Duan, Y. Yang, B. Zhang, New superjunction LDMOS with N-Type charges’ compensation layer. IEEE Electron Device Lett. 30(3), 305–307 (2009). https://doi.org/10.1109/LED.2009.2012396
B. Duan, Z. Cao, X. Yuan, S. Yuan, Y. Yang, New superjunction LDMOS breaking silicon limit by electric field modulation of buffered step doping. IEEE Electron Device Lett. 36(1), 47–49 (2015). https://doi.org/10.1109/LED.2014.2366298
W. Chen, B. Zhang, Z. Li, Optimization of super-junction SOI-LDMOS with a step doping surface-implanted layer. Semicond. Sci. Technol. 22(5), 464–470 (2007). https://doi.org/10.1088/0268-1242/22/5/002
B. Duan, Z. Cao, S. Yuan, Y. Yang, Complete 3D-reduced surface field superjunction lateral double-diffused MOSFET breaking silicon limit. IEEE Electron Device Lett. 36(12), 1348–1350 (2015). https://doi.org/10.1109/LED.2015.2493080
W. Zhang et al., Optimization and experiments of lateral semi-superjunction device based on normalized current-carrying capability. IEEE Electron Device Lett. 40(12), 1969–1972 (2019). https://doi.org/10.1109/LED.2019.2948198
Acknowledgements
This work was supported by Scientific Research Fund of Hunan Provincial Education Department (No. 19K001) The Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering, the School of Physics & Electronic Science, Changsha University of Science & Technology, Changsha, 410114, China
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Wu, L., Chen, J., Yang, H. et al. A Ultra-Low Specific On-Resistance and Extended Gate SJ LDMOS Structure. Trans. Electr. Electron. Mater. 22, 211–216 (2021). https://doi.org/10.1007/s42341-021-00302-7
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DOI: https://doi.org/10.1007/s42341-021-00302-7