CNTFET Based Ternary 1-Trit & 2-Trit Comparators for Low Power High-Performance Applications

Abstract

1-Trit and 2-Trit Ternary comparator circuits using Complementary Metal–Oxide–Semiconductor (CMOS) as well as Carbon Nanotube Field-Effect Transistor (CNTFET) is proposed and investigated for Low Power High-performance applications. The design and simulation are investigated and authenticated using Hailey Simulation Program with Integrated Circuit (HSPICE) with Predictive technology model (PTM) low power 32 nm metal gate/High-K/Strained-Si Model for CMOS and 32 nm Stanford Model for CNTFET. The CNTFET based design is compared with the CMOS design in terms of significant design aspects, specifically delay, Average Power consumption and Power delay product (PDP). A comparison is performed among CMOS and CNTFET based ternary comparator circuits which reveals that CNTFETs can lead to more efficient ternary circuits. In terms of delay and power consumption, the CNTFET based 1-Trit Ternary Comparator performs better than the CMOS based 1-Trit Ternary Comparator as the delay and Average power consumption are reduced by 89.7% and 57.3% in CNTFET type as compared to the CMOS based 1-Trit Ternary Comparator design. Similarly, in the case of the 2-Trit comparator, the CNTFET based design performs better than the CMOS-based design as the delay and Average power consumption are reduced by 88.7% and 42% in the CNTFET type.