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CNTFET Based 4-Trit Hybrid Ternary Adder-Subtractor for low Power & High-Speed Applications

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Abstract

To go through the phenomenon at nanoscale regimes, circuits using the CNTFETbased on Ternary Logic have been explored due to their constantly increasing application in high-speed low power designs. In this paper, 4-Trit Ternary Adder-Subtractor (TAS) using Complementary metal-oxide-semiconductor (CMOS) and Carbon Nanotube Field-Effect Transistor (CNFET) is proposed, which demonstrates the ternary addition and subtraction with a single circuit. The design style is based on conventional static CMOS implementation. The Fundamental ternary logic units are connected to achieve the required design. Therefore, prominence is given to the optimization of these fundamental units. The implementation and simulation are analyzed and validated using Hailey Simulation Program with Integrated Circuit (HSPICE) with PTM low power 32 nm metal gate / High-K / Strained-Si Model for CMOS and 32 nm Stanford Model for CNTFET. The CMOS based design is compared with the CNTFET design in terms of key design factors, namely average delay, power consumption and power delay product(PDP). The simulation results reveal that CNTFET based 4-Trit Ternary Adder-Subtractor accomplishes better results in comparison with CMOS based 4-Trit Ternary Adder-Subtractor design. When compared with CMOS-based 4-Trit TAS, it is found that in CNTFET based 4-Trit TAS the average delay and power consumption is improved by approximately 82% and 71% respectively.

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References

  1. Raychowdhury A, Roy K (2005) Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans Nanotechnol 4(2):168–179

    Article  Google Scholar 

  2. Wu XW, Prosser FP (1990) CMOS ternary logic circuits. IEE Proceedings G-Circuits. Devices and Systems 137(1):21–27

    Google Scholar 

  3. Etiemble D, Isreal M (1977) Implementation of ternary circuits with-binary integrated circuits. IEEE Transactions on Computers 12:1222–1233

    Article  Google Scholar 

  4. Baughman RH, Zakhidov AA, De Heer WA (2002) Carbon nanotubes--the route toward applications. Science. 297(5582):787–792

    Article  CAS  Google Scholar 

  5. International Technology Roadmap for Semiconductors (ITRS) (2015) Emerging Research Device Summary

  6. Singh A, Khosla M, Raj B (2015) Comparative analysis of carbon nanotube field effect transistors. In: 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE). IEEE, pp 552–555. Corpus ID: 3437512. https://doi.org/10.1109/GCCE.2015.7398601

  7. Chowdhury AH, Akhter N, Al Faisal A (2012) Performance analysis and development of self-consistent model of carbon nanotube field effect transistor (CNTFET). In: ProcGlobal Eng, Dhaka, Bangladesh, pp 1–9

  8. Moaiyeri MH, Mirzaee RF, Navi K, Hashemipour O (2011) Efficient CNTFET-based ternary full adder cells for nanoelectronics. Nano-Micro Letters 3(1):43–50

    Article  Google Scholar 

  9. McEuen PL, Fuhrer MS, Park H (2002) Single-walled carbon nanotube electronics. IEEE Trans Nanotechnol 1(1):78–85

    Article  Google Scholar 

  10. Wu J, Shen YL, Reinhardt K, Szu H, Dong B (2013) A nanotechnology enhancement to Moore’s law. Appl Computation Intell Soft Comput. https://doi.org/10.1155/2013/426962

  11. Ren Z, Lan Y, Wang Y (2012) Aligned carbon nanotubes: physics, concepts, fabrication and devices. Springer Science & Business Media. Springer Heidelberg, New York, Dordrecht and London. https://doi.org/10.1007/978-3-642-30490-3

  12. Bacon R (1960) Growth, structure, and properties of graphite whiskers. J Appl Phys 31(2):283–290

    Article  Google Scholar 

  13. Marani R, Perri AG (2016) A simulation study of analogue and logic circuits with CNTFETs. ECS J Solid State Sci Technol 5(6):M38–M43

    Article  CAS  Google Scholar 

  14. Quitoriano NJ, Kamins TI (2008) Integratable nanowire transistors. Nano Lett 8(12):4410–4414

    Article  CAS  Google Scholar 

  15. Mintmire JW, White CT (1998) Universal density of states for carbon nanotubes. Phys Rev Lett 81(12):2506–2509

    Article  CAS  Google Scholar 

  16. Singh A, Khosla M, Raj B (2016) Circuit compatible model for electrostatic doped Schottky barrier CNTFET. J Electron Mater 45(10):5381–5390

    Article  CAS  Google Scholar 

  17. Rani S, Singh B (2018) Investigation of Schottky barrier, conventional and tunnel carbon nanotube field effect transistor for low power design. J Nanoelectron Optoelectron 13(1):76–82

    Article  CAS  Google Scholar 

  18. Lin S, Kim YB, Lombardi F (2012) Design of a ternary memory cell using CNTFETs. IEEE Trans Nanotechnol 11(5):1019–1025

    Article  Google Scholar 

  19. Cho G, Lombardi F (2016) Design and process variation analysis of CNTFET-based ternary memory cells. Integration 54:97–108

    Article  Google Scholar 

  20. Zhang J, Lin A, Patil N, Wei H, Wei L, Wong HS, Mitra S (2012) Robust digital VLSI using carbon nanotubes. IEEE Trans Comput-Aided Design Integrated Circuits Syst 31(4):453–471

    Article  CAS  Google Scholar 

  21. Kumar H, Srivastava S, Singh B (2019) Comparative analysis of 6T, 7T conventional CMOS and CNTFET based SRAM cell design. Adv Sci Eng Med 11(1–2):3–10. American Scientific Publishers. https://doi.org/10.1166/asem.2019.2301

  22. Sridharan K, Gurindagunta S, Pudi V (2013) Efficient multi-ternary digit adder design in CNTFET technology. IEEE Trans Nanotechnol 12(3):283–287

    Article  CAS  Google Scholar 

  23. Keshavarzian P, Sarikhani R (2014) A novel CNTFET-based ternary full adder. Circuits Syst Signal Process 33(3):665–679

    Article  Google Scholar 

  24. Razi F, MoaiyeriMH RR, Mohammadi S (2019) A variation-aware ternary spin-hall assisted STT-RAM based on hybrid MTJ/GAA-CNTFET logic. IEEE Trans Nanotechnol 18:598–605. https://doi.org/10.1109/TNANO.2019.2918198

  25. Tamersit K (2020) Sub-10 nm junctionless carbon nanotube field-effect transistors with improved performance. AEU-Int J Electron Commun 124:153354

    Article  Google Scholar 

  26. Marani R, Perri AG (2020) Impact of technology on CNTFET- based circuits performance. ECS J Solid State Sci Technol 9(5):051001. Published on behalf of ECS by IOP Publishing Limited

  27. Moaiyeri MH, Nasiri M, Khastoo N (2016) An efficient ternary serial adder based on carbon nanotube FETs. Eng Sci Technol Int J 19(1):271–278. Elsevier

  28. Kumari A, Rani S, Singh B (2019) Parameterized comparison of Nanotransistors based on CNT and GNR materials: effect of variation in gate oxide thickness and dielectric constant. J Electron Mater 48(5):3078–3085

    Article  CAS  Google Scholar 

  29. Moghaddam M, Moaiyeri MH, Eshghi M (2017) Design and evaluation of an efficient Schmitt trigger-based hardened latch in CNTFET technology. IEEE Trans Device Mater Reliab 17(1):267–277. https://doi.org/10.1109/TDMR.2017.2665780

  30. Bala S, Khosla M (2018) Design and analysis of electrostatic doped tunnel CNTFET for various process parameters variation. Superlattice Microst 124:160–167. Elsevier. https://doi.org/10.1016/j.spmi.2018.10.007

  31. Shahrom E, Hosseini SA (2018) A new low power multiplexer based ternary multiplier using CNTFETs. AEU-Int J Electron Commun 93:191–207

    Article  Google Scholar 

  32. Bala S, Khosla M (2019) Design and performance analysis of low-power SRAM based on electrostatically doped tunnel CNTFETs. J Comput Electron 18(3):856–863

    Article  CAS  Google Scholar 

  33. Moaiyeri MH, Doostaregan A, Navi K (2011) Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Devices Syst 5(4):285–296

    Article  Google Scholar 

  34. Rani S, Kaur G, Lakha BS (2018) Ternary logic design approach-from CMOS to CNTFET. J Nanosci Nanoeng Appl 8(2):20–30

    CAS  Google Scholar 

  35. Doostaregan A, Moaiyeri MH, Navi K, Hashemipour O (2010) On the design of new low-power CMOS standard ternary logic gates. In 2010 15th CSI International Symposium on Computer Architecture and Digital Systems. IEEE:115-120

  36. Moaiyeri MH, Mirzaee RF, Doostaregan A, Navi K, Hashemipour O (2013) A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. IET Comput Digital Techniques 7(4):167–181

  37. Lin S, Kim YB, Lombardi F (2009) CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans Nanotechnol 10(2):217–225. https://doi.org/10.1109/TNANO.2009.2036845

  38. Gaikwad VT, Deshmukh PR (2015) Design of CMOS ternary logic family based on single supply voltage. In 2015 International Conference on Pervasive Computing (ICPC). IEEE: 1-6

  39. Samadi H, Shahhoseini A, Aghaei-liavali F (2017) A new method on designing and simulating CNTFET_based ternary gates and arithmetic circuits. Microelectron J 63:41–48

    Article  CAS  Google Scholar 

  40. Shin S, Jang E, Jeong JW, Park BG, Kim KR (2015) Compact design of low power standard ternary inverter based on OFF-state current mechanism using nano-CMOS technology. IEEE Trans Electron Devices 62(8):2396–2403

    Article  Google Scholar 

  41. Srivastava A, Venkatapathy K (1996) Design and implementation of a low power ternary full adder. VLSI design 4(1):75–81

    Article  Google Scholar 

  42. Douglas WJ (2012) The ternary manifesto. The university of IOWA department of Computer Science, http://www.cs.uiowa.edu/~jones/ternary/ standard ternary Logic.1-17

  43. Patcha K, Musala S, Vijayavardhan K, Sudha Vani Y, Srinivasulu A (2016) Carbon nano tube field effect transistors based ternary ex-OR and ex-NOR gates. Curr Nanosci 12(4):520–526

    Article  CAS  Google Scholar 

  44. Sujatha Y, Lakshmi VKNVS (2017) Applications of XOR gate using ternary logic. International journal of creative research thoughts (IJCRT), 5(4). ISSN 2320-2882:2450–2454

    Google Scholar 

  45. Mano MM, Ciletti MD (2013) Digital design: with an introduction to the verilog hdl

  46. Stanford University CNFET Model. http://nanostanford.edu/models.phpwebsite

  47. Predictive Technology Model. http://ptm.asu.edu/modelcard/LP/32nm_LP.pm

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Authors and Affiliations

  1. I.K.G. Punjab Technical University Jalandhar, Jalandhar, Punjab, 144001, India

    Suman Rani

  2. Baba Farid College of Engineering & Technolgy Bathinda, Bathinda, Punjab, 151001, India

    Suman Rani

  3. ACS Division, Centre for Development of Advanced Computing, (Ministry of Electronics and Information Technology (MEITy), Govt. of India), Mohali, 160071, India

    Balwinder Singh

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  1. Suman Rani
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Dr. Balwinder Singh Guided, concepts, Proof read and helped in Implementations Suman rani: written paper and concept implementation and written paper.

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Rani, S., Singh, B. CNTFET Based 4-Trit Hybrid Ternary Adder-Subtractor for low Power & High-Speed Applications. Silicon 14, 689–702 (2022). https://doi.org/10.1007/s12633-020-00911-6

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