Skip to main content

Advertisement

SpringerLink
Log in

FPGA Accelerated Parallel HsClone GA for Digital Circuit Configuration in CGP Format

  • Original Contribution
  • Published:
Journal of The Institution of Engineers (India): Series B Aims and scope Submit manuscript

Abstract

The embryonic fabric architecture has emerged recently for realizing the digital circuits having scope of self-repair with minimal resources. Digital circuit configuration data can be optimized using genetic algorithms (GA) in the design space. Further Cartesian Genetic programming (CGP) has evolved for improved representation of circuit configuration data. The design and implementation of PHsClone (Parallel Half-Sibling and Clone) GA are presented in this work for the purpose of producing design data in CGP format for digital systems realized on embryonic architecture. Due to computational complexity, GAs suffers from large convergence time, especially for evolving digital circuit design where search spaces are inherently large. Using parallel processing for HsClone algorithm on FPGA, configuration data or potential circuit solution can be generated at faster speed. The embryonic fabric on which the digital circuit is implemented can be self-repaired in case of fault. The CGP format of circuit configuration data enables the fault location at node or gate level. Also The CGP format of configuration data has advantage over LUT format as it does not increase linearly for larger modular circuits, e.g., 1-bit adder to 4-bit adder. The proposed PHsClone GA design is implemented on Xilinx Virtex-7. The PHsClone algorithm was tested on standard benchmark circuits like 1-bit adders and 2-bit comparators to build 4-bit adders and 8-bit comparators, as well as a safe mode sensing circuit used in-flight electronics. The simulation results show that a safe mode detection circuit can converge 37 times faster using four in-line PHsClone GA (parallel threads) than using a single HsClone GA. In comparison, a 1-bit adder can converge 10 times faster and a 2-bit comparator can converge 3 times faster.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

Similar content being viewed by others

Data Availability

Data sharing not applicable to this article as no datasets were generated or analyzed during the current study.

References

  1. Z. Vasicek, L. Sekanina, Evolutionary approach to approximate digital circuits design. IEEE Trans. Evol. Comput. 19(3), 432–444 (2015)

    Article  Google Scholar 

  2. A. AL-Marakeby, FPGA on FPGA: implementation of fine-grained parallel genetic algorithm on field programmable gate array. Int. J. Comput. Appl. 80(6), 29–32 (2013). https://doi.org/10.5120/13867-1725

    Article  Google Scholar 

  3. B.I. Hounsell, T. Arslan, R. Thomson, Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform. Soft. Comput. 8(5), 307–317 (2004). https://doi.org/10.1007/s00500-003-0287-x

    Article  Google Scholar 

  4. L. Guo, D.B. Thomas, C. Guo, W. Luk, Automated framework for FPGA-based parallel genetic algorithms, in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 (2014). https://doi.org/10.1109/FPL.2014.6927501

  5. M. Psarakis, A. Dounis, A. Almabrok, S. Stavrinidis, G. Gkekas, An FPGA-based accelerated optimization algorithm for real-time applications. J. Signal Process. Syst. 92(10), 1155–1176 (2020). https://doi.org/10.1007/s11265-020-01522-5

    Article  Google Scholar 

  6. S.P. Hoseini Alinodehi, S. Moshfe, M. Saber Zaeimian, A. Khoei, K. Hadidi, High-speed general purpose genetic algorithm processor. IEEE Trans. Cybern. 46(7), 1551–1565 (2016). https://doi.org/10.1109/TCYB.2015.2451595

    Article  Google Scholar 

  7. S.D. Scott, A. Samal, S. Seth, HGA: A hardware-based genetic algorithm, in Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays (FPGA’95) (1995)

  8. L. Guo, C. Guo, D.B. Thomas, W. Luk, Pipelined genetic propagation, in Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, pp. 103–110 (2015). https://doi.org/10.1109/FCCM.2015.64

  9. J. Esch, Toward robust integrated circuits: the embryonics approach. Proc. IEEE 88(4), 514–515 (2000). https://doi.org/10.1109/JPROC.2000.842997

    Article  Google Scholar 

  10. G. Tempesti, D. Mange, P.A. Mudry, J. Rossier, A. Stauffer, Self-replication for reliability: bio-inspired hardware and the embryonics project, in Proceedings of the 3rd Conference on Computing Frontiers, CF’06, pp. 199–206 (2006). https://doi.org/10.1145/1128022.1128050

  11. L. Prodan, M. Udrescu, M. Vladutiu, Self-repairing embryonic memory arrays, in Proceedings - 2004 NASA/DoD Conference on Evolvable Hardware, pp. 130–137 (2004). https://doi.org/10.1109/EH.2004.1310821

  12. C. Reis, J.A. Tenreiro Machado, J. Boaventura Cunha, E.J. Solteiro Pires, Evolutionary computation in the design of logic circuits, in Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, pp. 1664–1669 (2007). https://doi.org/10.1109/ICSMC.2007.4413699

  13. Z. Vasicek, Bridging the gap between evolvable hardware and industry using cartesian genetic programming. Complex. Comput. 28, 39–55 (2018). https://doi.org/10.1007/978-3-319-67997-6_2

    Article  Google Scholar 

  14. G. Malhotra, P. Duraiswamy, J.K. Kishore, Evolving embryonic cell for combinational circuits using cartesian genetic programming, in Proceedings of CONECCT 2021: 7th IEEE International Conference on Electronics, Computing and Communication Technologies (2021). https://doi.org/10.1109/CONECCT52877.2021.9622686

  15. M. Abbasi et al., An efficient parallel genetic algorithm solution for vehicle routing problem in cloud implementation of the intelligent transportation systems. J. Cloud Comput. (2020). https://doi.org/10.1186/s13677-020-0157-4

    Article  Google Scholar 

  16. W.N. Abdullah, S.A. Alagha, A Parallel adaptive genetic algorithm for job shop scheduling problem. J. Phys. Conf. Ser. (2021). https://doi.org/10.1088/1742-6596/1879/2/022078

    Article  Google Scholar 

  17. Z. Zhu, D.J. Mulvaney, V.A. Chouliaras, Hardware implementation of a novel genetic algorithm. Neurocomputing 71(1–3), 95–106 (2007). https://doi.org/10.1016/j.neucom.2006.11.031

    Article  Google Scholar 

  18. D.J. Walker, M.J. Craven, Identifying good algorithm parameters in evolutionary multi- and many-objective optimisation: a visualisation approach. Appl. Soft Comput. J. 88, 105902 (2020). https://doi.org/10.1016/j.asoc.2019.105902

    Article  Google Scholar 

  19. L. Hong, J.H. Drake, J.R. Woodward, E. Özcan, A hyper-heuristic approach to automated generation of mutation operators for evolutionary programming. Appl. Soft Comput. J. 62, 162–175 (2018). https://doi.org/10.1016/j.asoc.2017.10.002

    Article  Google Scholar 

  20. A.P. Engelbrecht, Computational Intelligence: An Introduction (Wiley, 2007). https://books.google.co.in/books?id=IZosIcgJMjUC

  21. M.F. Torquato, M.A.C. Fernandes, High-performance parallel implementation of genetic algorithm on FPGA. Circuits Syst. Signal Process. 38(9), 4014–4039 (2019). https://doi.org/10.1007/s00034-019-01037-w

    Article  Google Scholar 

  22. L. Guo, A.I. Funie, D.B. Thomas, H. Fu, W. Luk, Parallel genetic algorithms on multiple FPGAs. ACM SIGARCH Comput. Archit. News 43(4), 86–93 (2016). https://doi.org/10.1145/2927964.2927980

    Article  Google Scholar 

  23. G. Malhotra, V. Lekshmi, S. Sudhakar, S. Udupa, Implementation of threshold comparator using cartesian genetic programming on embryonic fabric. Adv. Intell. Syst. Comput. 939, 93–102 (2019). https://doi.org/10.1007/978-3-030-16681-6-10

    Article  Google Scholar 

  24. G. Malhotra, Cartesian genetic programming approach for embryonic fabric architecture, in Proceedings of the 6th International Conference on Information Communication and Management, ICICM 2016, pp. 285–290 (2016). https://doi.org/10.1109/INFOCOMAN.2016.7784259

  25. C. Reis, J. Tenreiro Machado, An evolutionary approach to the synthesis of combinational circuits. J. Adv. Comput. Intell. Intell. Inform. 8(5), 507–513 (2004)

    Article  Google Scholar 

Download references

Funding

No funding was received for conducting this study.

Author information

Authors and Affiliations

  1. U R Rao Satellite Centre, Indian Space Research Organization, Old Airport Road, Bangalore, Karnataka, 560017, India

    Gayatri Malhotra & J. K. Kishore

  2. Department of Electronics and Communication Engineering, M.S. Ramaiah University of Applied Sciences, 4th Phase Peenya, Bangalore, Karnataka, 560058, India

    Gayatri Malhotra & Punithavathi Duraiswamy

Authors
  1. Gayatri Malhotra
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Punithavathi Duraiswamy
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. J. K. Kishore
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Gayatri Malhotra.

Ethics declarations

Conflict of interest

The authors have no competing interests to declare that are relevant to the content of this article.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Malhotra, G., Duraiswamy, P. & Kishore, J.K. FPGA Accelerated Parallel HsClone GA for Digital Circuit Configuration in CGP Format. J. Inst. Eng. India Ser. B 104, 1079–1089 (2023). https://doi.org/10.1007/s40031-023-00918-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s40031-023-00918-8

Keywords

Search

Navigation