Skip to main content
SpringerLink
Log in

A Probabilistic Tabu Search State Assignment Algorithm for Area and Power Optimization of Sequential Circuits

  • Research Article-Computer Engineering and Computer Science
  • Published:
Arabian Journal for Science and Engineering Aims and scope Submit manuscript

Abstract

State assignment is the most critical step in the synthesis and optimization of sequential circuits as it significantly impacts sequential circuits area and power. Due to the high complexity of the state assignment problem and the ineffectiveness of existing deterministic algorithms in generating good solutions, evolutionary algorithms can be employed to obtain more effective state assignment solutions. In this paper, we propose a probabilistic tabu search (PTS) state assignment algorithm that is employed for the optimization of area and power of sequential circuits. The proposed algorithm is based on tabu search with the addition of exploiting code swap probabilities to prune the search space more effectively. Code swap probabilities are updated dynamically during the execution of the algorithm in such a way that code swaps that result in relatively inferior solutions will be assigned lower probabilities while those that result in good solutions will be assigned higher probabilities. In addition, tabu list size is changed dynamically during execution to help the algorithm get out of local minima. Based on experimental results, we show that the proposed PTS state assignment algorithm is more effective than all existing state assignment algorithms as it generates state assignment solutions with significantly lower area and power.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3

Similar content being viewed by others

References

  1. Leiserson, C.E.; Saxe, J.B.: Optimizing synchronous systems. J. VLSI Comput. Syst. 1, 41–67 (1983)

    MATH  Google Scholar 

  2. El-Maleh, A.; Marchok, T.; Rajski, J.; Maly, W.: Behavior and testability preservation under the retiming transformation. IEEE Trans. Comput. Aided Des. 16, 528–543 (1997). May

    Article  Google Scholar 

  3. DeMicheli, G.; BraytonR. K. Brayton, R.K.; Sangiovanni Vincenteli, A.: Optimal state assignment for finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4, 269–285 (1985)

    Article  Google Scholar 

  4. Villa, T.; Sangiovanni-Vincentelli, A.: Nova: state assignment of finite state machines for optimal two-level logic implementations. In: 26th ACM/IEEE Conference on Design Automation Conference, pp. 327–332 (1989)

  5. Devadas, S.; Ma, H.T.; Newton, A.R.; Sangiovanni-Vincentelli, A.: MUSTANG: state assignment of finite state machines for optimal multilevel logic implememations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7, 1290–1300 (1988)

    Article  Google Scholar 

  6. Lin, B.; Newton, A.R.: Synthesis of multiple-level logic from symbolic high-level description languages. In: IFIP International Conference on Very Large Scale Integration, pp. 187–196 (1989)

  7. Du, X.; Hachtel, G.; Lin, B.; Newton, A.R.: MUSE: a multilevel symbolic encoding algorithm for state assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10, 28–38 (1991)

    Article  Google Scholar 

  8. Salauyou, V.; Grzes, T.: FSM state assignment methods for low-power design. In: 6th International Conference on Computer Information Systems and Industrial Management Applications, pp. 345–350 (2007)

  9. Sagahyroon, A.; Aloul, F.A.; Sudnitson, A.: Low power state assignment using ILP techniques. In: 15th IEEE Mediterranean Electrotechnical Conference, pp. 850–855 (2010)

  10. Shiue, W.-T.: Power/area/delay aware FSM synthesis and optimization. Microelectron. J. 36, 147–162 (2005)

    Article  Google Scholar 

  11. El-Maleh, A.H.: Majority-based evolution state assignment algorithm for area and power optimization of sequential circuits. IET Comput. Digit. Tech. 10, 30–36 (2016)

    Article  Google Scholar 

  12. El-Maleh, A.H.: A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization. Integr. VLSI J. 56, 32–43 (2017)

    Article  Google Scholar 

  13. Amaral, J.; Turner, K.; Ghosh, J.: Designing genetic algorithm for state assignment problem. IEEE Trans. Syst. Man Cybern. 25, 659–694 (1995)

    Article  Google Scholar 

  14. Almaini, A.E.A.; Miller, J.F.; Thomson, P.; Billina, S.: State assignment of finite state machines using a genetic algorithm. IEE Comput. Dig. Tech. 142, 279–286 (1995)

    Article  Google Scholar 

  15. Xia, Y.; Almaini, A.E.A.: Genetic algorithm based state assignment for power and area optimization. IEE Comput. Dig. Tech. 149, 128–133 (2002)

    Article  Google Scholar 

  16. Chattopadhyay, S.; Chetry, A.; Biswas, S.: State assignment and selection of types and polarities of flip-flops, for finite state machine synthesis. In: IEEE INDICON, pp. 27–30 (2004)

  17. El-Maleh, A.; Sait, S.M.; Khan, F.N.: Finite state machine state assignment for area and power minimization. In: IEEE International Symposium on Circuits and Systems, pp. 5303–5306 (2006)

  18. Pradhan, S.N.; Kumar, M.T.; Chattopadhyay, S.: Integrated power-gating and state assignment for low power FSM synthesis. In: IEEE Computer Society Annual Symposium on VLSI, pp. 269–274 (2008)

  19. Chaudhury, S.; Sistla, K.T.; Chattopadhyay, S.: Genetic algorithm-based FSM synthesis with area-power trade-offs. Integr. VLSI J. 42, 376–384 (2009)

    Article  Google Scholar 

  20. Al Jassani, B.A.; Urquhart, N.; Almaini, A.E.A.: State assignment for sequential circuits using multi-objective genetic algorithm. IET Comput. Digit. Tech. 5, 296–305 (2011)

    Article  Google Scholar 

  21. Aly, W.M.: Solving the state assignment problem using stochstic search aided with simulated annealing. Am. J. Eng. Appl. Sci. 2, 703–707 (2009)

    Article  Google Scholar 

  22. Yang, M.: State assignment for finite state machine synthesis. J. Comput. 8, 1406–1410 (2013)

    Google Scholar 

  23. Khan, F.N.: FSM state assignment for area, power and testability using non-deterministic evolutionary heuristics. Master’s thesis, KFUPM, Saudi Arabia (2005)

  24. Oughali, F.C.; Sait, S.M.; Arafeh, A.M.: FSM state-encoding for area and power minimization using simulated evolution algorithm. J. Appl. Res. Technol. 10, 845–858 (2012)

    Google Scholar 

  25. El-Maleh, A.H.; Sheikh, A.T.; Sait, S.M.: Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits. Appl.Soft Comput. 13, 4832–4840 (2013)

    Article  Google Scholar 

  26. El-Maleh, A.H.; Sait, S.M.; Bala, A.: State assignment for area minimization of sequential circuits based on cuckoo search optimization. Comput. Electr. Eng. 44, 13–23 (2015)

    Article  Google Scholar 

  27. El-Maleh, A.H.: Systems and Method for Optimizing State Encoding. US Patent (2018)

  28. Tao, Y.; Zhang, L.; Wang, Q.; et al.: A multi-population evolution stratagy and its application in low area/power FSM synthesis. Nat. Comput. 18, 139–161 (2019)

    Article  MathSciNet  Google Scholar 

  29. Chyzy, M.; Kosinski, W.: Evolutionary algorithm for state assignment of finite machines. In: Euromicro Symposium on Digital System Design, pp. 359–362 (2002)

  30. Nedjah, N.; de Macedo Mourelle, L.: Evolutionary synthesis of synchronous finite state machines. In: International Conference on Computer Engineering and Systems, pp. 19–24 (2006)

  31. http://www.cbl.ncsu.edu:16080/benchmarks/LGSynth89/fsmexamples

  32. Sentovich, E.M.; Singh, K.J.; Lavagno, L.; Moon, C.; Murgai, R.; Saldanha, A.; Savoj, H.; Stephan, P.R.; Brayton, R.K.; Sangiovanni-Vincentelli, A.: SIS: a system for sequential circuit synthesis. EECS Department, University of California, Berkeley. http://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/ERL-92-41.pdf

  33. Ruxton, G.D.: The unequal variance t-test is an underused alternative to Student’s t-test and the Mann–Whitney U test. Behav. Ecol. 17, 688–690 (2006)

    Article  Google Scholar 

Download references

Acknowledgements

This work is supported by King Fahd University of Petroleum & Minerals.

Author information

Authors and Affiliations

  1. Computer Engineering Department, KFUPM, Dhahran, Saudi Arabia

    Aiman H. El-Maleh

Authors
  1. Aiman H. El-Maleh
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Aiman H. El-Maleh.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

El-Maleh, A.H. A Probabilistic Tabu Search State Assignment Algorithm for Area and Power Optimization of Sequential Circuits. Arab J Sci Eng 45, 6273–6285 (2020). https://doi.org/10.1007/s13369-020-04697-y

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s13369-020-04697-y

Keywords

Search

Navigation