Abstract
This work presents silicon-on-insulator (SOI) junction-less FETs (C-JLFET) with a pyramid P+ area within the buried oxide region (PP-JLFET). The Silvaco software analysis shows that the PP-JLFET with P+ area within the BOX layer has improved the ION/IOFF ratio of ~ 1010 and causes the proposed device to be suitable for logic operations. The principal concept of this paper concentrates on enhancing the depletion region for obtaining a smaller off-current (IOFF) ~ 10–15. Although the on-current (ION) reduced slightly, but this decrement is very small value. Also, another purpose is to achieve a better self-heating effect (SHE), which is obtained by embedding a silicon pyramid P+ area with a larger thermal conductivity than the buried oxide region. SHE improves from 308 to 325 K in the proposed device versus the conventional JLFET. Effects including carrier density, lattice temperature, SHE, and kink effect have been investigated, and the PP-JLFET results demonstrate that the proposed device improves the device characteristics versus C-JLFET.
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MB: Conceptualization, Writing—original draft, Software. AAO: review and editing, Software. AA: Supervision—review and editing. MH: review and editing, Software.
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Bolokian, M., Orouji, A.A., Abbasi, A. et al. Pyramid P+ area in SOI junction-less MOSFET for logic applications: DC investigation. Appl Nanosci 13, 5711–5717 (2023). https://doi.org/10.1007/s13204-023-02808-3
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DOI: https://doi.org/10.1007/s13204-023-02808-3