Abstract
A superjunction (SJ) insulated gate bipolar transistor (IGBT) featuring an embedded self-biased (ESB) n-type metal–oxide–semiconductor field-effect transistor (NMOS) between the P-pillar and the emitter is proposed and simulated. During the on-state, the NMOS is turned off to maintain high conductivity modulation, achieving a relatively low on-state voltage (Von). The P-pillar is connected to the emitter through the NMOS in the blocking state, which prevents premature breakdown at the corner of the trench gate. Consequently, a high breakdown voltage (BV) is ensured. During the turn-off period, the embedded self-biased NMOS turns on adaptively with the increasing potential of the P-pillar. An extra path is formed to extract excessive carriers in the drift region, thereby minimizing turn-off losses (Eoff). Numerical simulations show that a 48.9% reduction in Von is achieved for the proposed IGBT when compared with the conventional (Con.) SJ IGBT at the same Eoff. Furthermore, the Eoff of the proposed IGBT is reduced by 23.8% and the BV is improved by 21.5% compared to the SJ IGBT with a floating P-pillar (FP SJ IGBT) at the same Von.
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Acknowledgements
This work was supported in part by the Hunan Provincial Natural Science Foundation of China under Grant 2021JJ30738, in part by the Scientific Research Fund of Hunan Provincial Education Department under Grant 19K001, and in part by the Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering’s Open Fund Project-2020 under Grant 202016.
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Wu, L., Zhang, B., Deng, G. et al. A Superjunction Insulated Gate Bipolar Transistor with Embedded Self-biased N-Type Metal–Oxide–Semiconductor Field-Effect Transistor. J. Electron. Mater. 52, 2177–2184 (2023). https://doi.org/10.1007/s11664-022-10148-1
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DOI: https://doi.org/10.1007/s11664-022-10148-1