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Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

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Abstract

In this paper, a novel Super Junction (SJ) Lateral Double-diffused MOSFET (LDMOS) is proposed. The two sides of the device substrate are connected with source-drain electrodes through ohmic contacts, so that the lateral voltage of the substrate is the same as the SJ layer, and they are independently depleted, therefore the SJ layer forms a more ideal rectangular electric field distribution. The surface of the substrate is completely depleted by the extended P-well and N buffer layer, forming an electric field distribution similar to the SJ layer, making the upper and lower potentials of the substrate surface equal. After the two layers are in contact, the electric field distribution of SJ layer will not be changed by the substrate, and finally the SAD effect can be completely eliminated. Simulation results show that the breakdown voltage (BV) of the conventional SJ-LDMOS device with N-type buffer layer is 362.5 V when the drift region length is 20 μm, and the specific on-resistance (Ron,sp) is 29.04 mΩ·cm2. Under the same drift region length, the new SJ-LDMOS has a BV of 470.7 V and a Ron,sp of 11.28 mΩ·cm2. The new device can reduce the Ron,sp by 61.16% while increasing the BV of 108.2 V. Finally, the figure of merit (FOM) value was increased by 339%. The fabrication process of the proposed device is compatible with the current mainstream silicon-based processes with relatively low-cost process difficulty, which is more conducive to high power electron applications and productions.

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References

  1. Houadef A, Djezzar B (2021) Hot carrier degradation in triple-RESURF LDMOS with trenched-gate. IEEE 32nd International Conference on Microelectronics (MIEL), pp 141–144. https://doi.org/10.1109/MIEL52794.2021.9569100

  2. Cheng J, Li P, Chen W, Yi B, Chen XB (2018) Simulation study of a super-junction deep-trench LDMOS with a trapezoidal trench. IEEE J Electron Devices Soc 6:1091–1096. https://doi.org/10.1109/JEDS.2018.2867344

    Article  CAS  Google Scholar 

  3. He N, Zhang S, Zhu X, Li X, Wang H, Zhang W (2020) A 0. 25µm700V BCD technology with ultra-low specific on-resistance SJ-LDMOS. 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp 419–422. https://doi.org/10.1109/ISPSD46842.2020.9170046

  4. Yong I, Park C, Salama CAT (2006) "Super Junction LDMOS Transistors - Implementing super junction LDMOS transistors to overcome substrate depletion effects,“. IEEE Circuits Devices Mag 22(6):10–15. https://doi.org/10.1109/MCD.2006.307271

    Article  Google Scholar 

  5. Tsai J, Hu H (2016) New super-junction LDMOS based on poly-si thin-film transistors. IEEE J Electron Devices Soc 4(6):430–435. https://doi.org/10.1109/JEDS.2016.2600253

  6. Guo S, Huang H, Chen XB (2018) Study of the SOI LDMOS with low conduction loss and less gate charge. IEEE Trans Electron Devices 65(4):1645–1649. https://doi.org/10.1109/TED.2018.2806921

  7. Zhang W, Zhan Z, Yu Y, Cheng S, Gu Y, Zhang S, Luo X, Li Z, Qiao M, Li Z, Zhang B (2017) Novel superjunction LDMOS (> 950 V) with a thin layer SOI. IEEE Electron Device Lett 38(11):1555–1558. https://doi.org/10.1109/LED.2017.2751571

  8. Duan B, Cao Z, Yuan X, Yuan S, Yang Y (2015) New superjunction LDMOS breaking silicon limit by electric field modulation of buffered step doping. IEEE Electron Device Lett 36(1):47–49. https://doi.org/10.1109/LED.2014.2366298

  9. Mishra A, Kumar BS, Somayaji J, Shrivastava M, Gupta A (2020) Impact of space charge modulation on superjunction-LDMOS. 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp 68–69. https://doi.org/10.1109/VLSI-TSA48913.2020.9203659

  10. Duan B, Li M, Dong Z, Wang Y, Yang Y (2019) New super-junction LDMOS breaking silicon limit by multi-ring assisted depletion substrate. IEEE Trans Electron Devices 66(11):4836–4841. https://doi.org/10.1109/TED.2019.2939233

  11. Sentaurus Device User Guide, Synopsys, Mountain View, CA, USA

  12. Park I-Y, Choi Y-K, Ko K-Y, Yoon C-J, Kim Y-S, Kim M-Y, Kim H-T, Lim H-C, Kim N-J, Yoo K-D (2009) Implementation of buffered super-junction LDMOS in a 0.18um BCD Process. In: Proc. 21st Int. Symp. Power Semicond. Devices IC’s (ISPSD), Barcelona, Spain. pp 192–195. https://doi.org/10.1109/ISPSD.2009.5158034

  13. Qiao M, Li Y, Zhou X, Li Z, Zhang B (2014) A 700- V junction-isolated triple RESURF LDMOS With N-type top layer. IEEE Electron Device Lett 35(7):774–776. https://doi.org/10.1109/LED.2014.2326185

  14. Zhang W, He J, Cheng S, Zhang S, He B, Qiao M, Li Z, Zhang B (2020) Novel self-modulated lateral superjunction device suppressing the inherent 3-D JFET effect. IEEE Electron Device Lett 41(9):1392–1395. https://doi.org/10.1109/LED.2020.3009994

  15. Liang L, Huang H, Chen X (2016) A variation laterl doping layer and lightly doped region compensated superjunction LDMOS. IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp 120–123. https://doi.org/10.1109/EDSSC.2016.7785224

  16. Guo S, Cheng J, Chen XB (2019) IEEE 13th International Conference on Power Electronics and Drive Systems (PEDS), pp 1–3. https://doi.org/10.1109/PEDS44367.2019.8998889

  17. Cao Z, Jiao L (2020) Superjunction LDMOS with dual gate for low on-resistance and high transconductance. IEEE J Electron Devices Soc 8:890–896. https://doi.org/10.1109/JEDS.2020.3011929

    Article  CAS  Google Scholar 

  18. Wu L, Ding Q, Chen J (2020) Improved deep trench super-junction LDMOS breakdown voltage by shielded silicon-insulator-silicon capacitor. Silicon 13(10):3441–3446. https://doi.org/10.1007/s12633-020-00771-0

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Acknowledgements

This work was supported by the National Natural Science Foundation of China (NSFC) under Grant No. 61671343.

Funding

The work has received financial support from National Natural Science Foundation of China (NSFC).

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Authors and Affiliations

  1. School of Microelectronics, Xidian University, 710071, Xi’an, China

    Shunwei Zhu, Hujun Jia & Yintang Yang

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  1. Shunwei Zhu
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  2. Hujun Jia
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Contributions

Shunwei Zhu: Writing-Original draft preparation, Data curation, Writing-Reviewing Editing, Software and Validation;

Hujun Jia: Project administration and Formal analysis;

Yintang Yang: Supervision.

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Correspondence to Shunwei Zhu.

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Zhu, S., Jia, H. & Yang, Y. Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect. Silicon 15, 1443–1450 (2023). https://doi.org/10.1007/s12633-022-02113-8

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