Design and Analysis of 18 nm FinFET Device with High Density Meshing for High-speed and Ultra-low Power Applications

Abstract

Although the performance and power consumption of VLSI circuits have increased as a result, the designs’ dependability has worsened. Circuits become more sensitive when technology scales down due to a decrease in noise barrier and an increase in uncertainty from various sources of variability. Three-dimensional electrical devices such as double gate, tri-gate, and nanowire field-effect transistors (FETs) provide an alternate way by better electrostatically regulating the device channel. One at the source/channel region and the other at the drain/channel region, advanced transistors have dual metallurgical junctions. A high doping profile at these junctions is required to scale semiconductor devices below 20 nm. This study presents the results of simulations for a unique form of FinFET for high-speed applications with germanium composition and gate and source/drain connections. According to benchmarking data, when the current density of FinFETs grows, the short-channel behaviour improves. FinFETs with a high aspect ratio provide more current per unit area with fewer horizontal geometry constraints, making them appropriate for circumstances when conventional scaling has reached its physical limits. The proposed FinFET at the 18 nm technology node increases low-power and high-frequency performance, according to the findings of the trials.