Abstract
The present manuscript has proposed a capacitance-based model of dual material gate charge plasma-based vertically t-shaped Tunnel Field Effect Transistor (DMG V-tTFET) with spacer regions. The surface potential model, which modulates terminal capacitance and the drain current model is used to analyse the Poisson Equation (PE). For modelling the n-type channel, the inclusions are an enhancement-mode, accumulated charges, and ionized impurity charge carriers. The spacer region’s surface potential and channel region potential are inspected with modelling whose outcomes are authenticated by the simulations in the Silvaco TCAD software for various boundary conditions. The potential model is found by allocating the proposed device into ten distinct units and applying the 1-Dimensional (1-D) and 2-Dimensional (2-D) PE in their respective sections. To resolve the PEs for different sections, the parabolic approximation method is employed. The impact of geometrical variety, for instance, the spacer length and tunnelling width are analysed with dependence upon the electrical characteristics of DMG V-tTFET. The surface potential of greater than 0.75 V at a power supply voltage of 0.5 V is attributed to the establishment of an energy barrier in the channel with optimal device parameters.
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Prabin Kumar Bera: Conceptualization, Methodology, simulation and original draft preparation.
Rajib Kar: Investigation, reviewing and editing.
Durbadal Mandal: Final reviewing and editing.
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Bera, P.K., Kar, R. & Mandal, D. Modelling and Analysis of Dual Material Gate Charge Plasma Based Vertical t-shaped TFET. Silicon 14, 7667–7676 (2022). https://doi.org/10.1007/s12633-021-01518-1
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DOI: https://doi.org/10.1007/s12633-021-01518-1