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Structural Innovation for Better MOSFET Performance Suitable for Low Power Application

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Abstract

In this work, an innovative architecture of gate underlap junctionless double-gate MOSFET has been introduced with the idea of using triangular oxide layers to control the electric field near the drain side. A two-dimensional analytical model for the device has been developed based on 2D Poisson’s equation. We have applied Schwartz-Christoffel transformation to model the gate capacitance in the overlap region and conformal mapping to model the fringing electric flux in the gate underlap region and derived exclusive expressions for central potential, drain current, threshold voltage and subthreshold slope subsequently. TCAD tools have been adopted to validate our model. The results emphasize the effects of various device dimensions, especially the maximum oxide thickness and underlap length on various device parameters. The model is able to predict the impact of trapped charges on various device parameters. The structure exhibits excellent control over short channel effects and good designing flexibility obtained by varying the oxide geometry. We have also presented an application of the structure in the form of a CMOS inverter that yields promising results for low-power applications.

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  1. Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, West Bengal, 700032, India

    Saptarshi Maiti, Arpan De & Subir Kumar Sarkar

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  1. Saptarshi Maiti
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  2. Arpan De
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Maiti, S., De, A. & Sarkar, S.K. Structural Innovation for Better MOSFET Performance Suitable for Low Power Application. Silicon 14, 6219–6231 (2022). https://doi.org/10.1007/s12633-021-01390-z

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