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Virtually Doped Schottky Buried Metal Layer Planar Junctionless FET for SCE Suppression at sub-28nm Technology Nodes

Design, Simulation and Performance Investigation

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Abstract

Herein we introduce and investigate a new architectural design strategy for planar single gate field effect transistors (SG-FETs) that delivers advantages from all fronts of design, fabrication and performance perspectives. The amalgamation of schottky buried metal layer (BML) and charge plasma (CP) mechanism of doping in planar single gate architecture yields a novel type of FET called as CP-BML FET. Owing to the schottky BML induced depletion region created on the bottom side of device layer reduces effective device layer thickness (TSi) suppressing short channel effects (SCEs) including drain induced barrier lowering (DIBL) and threshold voltage roll-off. The proposed FET has been analyzed for DC and RF performance figure of merits (FOMs) and compared to counter part state of the art technologies with reference to ITRS performance projections. The proposed FET is also investigated the performance FOMs on for criticality of physical parameters including gate length (Lg), device layer thickness (TSi), BML workfunction (ϕBML). The ION and IOFF for proposed device at Lg = 20nm read at 730μ A/μ m and 7 × 10− 2 pA/μ m respectively. RF performance analysis reveal transition frequency (ft) of 390 GHz with SS \(\simeq \ \text {75mV/dec}\) coherent with ITRS performance projections. It is found that ultra scaled (7 nm) proposed device exhibits intrinsic delay τ of 0.6 ps which is superior to ITRS projections of 1.71 ps at 28 nm technology node. The proposed device yields Pdyn of 0.248 fJ/μ m at Lg= 7nm implicating it to be potential candidate for low power with high performance application requirements.

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Acknowledgments

The authors would like to thank head of the department, Department of Electronics and Communication Engineering, Malaviya National Institute of Technology for providing necessary support for carrying out the simulation work.

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No funding was received for this work.

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Authors and Affiliations

  1. Department of Electronics and Communucation Engineering, Malaviya National Institute of Technology Jaipur, Rajasthan, 302017, India

    Nawaz Shafi, Aasif Mohammad Bhat, Jaydeep Singh Parmaar, Ankita Porwal, Chitrakant Sahu & C. Periasamy

Authors
  1. Nawaz Shafi
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  2. Aasif Mohammad Bhat
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  3. Jaydeep Singh Parmaar
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  4. Ankita Porwal
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  5. Chitrakant Sahu
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  6. C. Periasamy
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Contributions

The main conception of this work is brainchild of N. Shafi (Author 1). A. M. Bhat, J. S. Parmar and A. Powral provided the necessary support regarding simulation and data interpretation. C. Sahu and C. Periasamy supervised the work and made important discussions and modifications to the final manuscript.

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Correspondence to Nawaz Shafi.

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Shafi, N., Bhat, A.M., Parmaar, J.S. et al. Virtually Doped Schottky Buried Metal Layer Planar Junctionless FET for SCE Suppression at sub-28nm Technology Nodes. Silicon 14, 4619–4631 (2022). https://doi.org/10.1007/s12633-021-01242-w

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  • DOI: https://doi.org/10.1007/s12633-021-01242-w

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