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Proposal of Charge Plasma Based Recessed Source/Drain Dopingless Junctionless Transistor and its Linearity Distortion Analysis for Circuit Applications

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Abstract

Linearity and intermodulation distortion (IMD) analysis examined major reliability issues that arise due to the non-linear behavior of the devices in analog/RF circuit applications. In this paper, by means of virtually doped (dopingless), a distinctive influence of charge-plasma (CP) is proposed on novel dual metal gate (DMG; control and screen gate) recessed source/drain (Re S/D) transistor; envisaged as recessed source/drain dopingless junctionless transistor (Re S/D DLJLT). Re S/D structure diminishes series resistance without any accretion of the gate-drain Miller capacitance resulting in a better drive current (ION). DC and analog characteristics have been further improved by adopting CP conception for induction of N+ S/D region owing to favorably well-chosen metal work function electrodes. The main intent of this paper is to appraise the linearity and IMD performance characteristics of the Re S/D DLJLT using 2-D numerical calculations and scrutinize the distinction with recessed source/drain junction transistor (Re S/D JT) with identical dimensions. Device linearity parameters comprise of transconductance (Gm1) and its higher order coefficients (Gm2 and Gm3), second and third order voltage and input intercept point (VIP2, VIP3, and IIP3) third order IMD, and 1 − dB compression point (1 − dBCP) which are based on possible structural and control to screen gate length ratios (CSLR) variations in both devices. The influences of parametric modifications on linearity Figure of merits (FOMs) explore optimum bias point by investigating optimum structural with CSLR variations. The detailed investigation of linearity FOMs of the impact on different device engineering has been carried out. The obtained outcomes divulge that proposed device delivers appreciably enhanced linearity FOMs as compared to Re S/D JT.

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References

  1. Moore, GE (1965) "Cramming more components onto integrated circuits." 114–117

  2. Schaller RR (1997) Moore's law: past, present and future. IEEE Spectr 34(6):52–59

    Article  Google Scholar 

  3. Doris, B, et al (2002) "Extreme scaling with ultra-thin Si channel MOSFETs." Digest. International Electron Devices Meeting, IEEE

  4. Choi, YK, et al (1999) "Ultra-thin body SOI MOSFET for deep-sub-tenth micron era." International Electron Devices Meeting 1999. Technical Digest (Cat. No. 99CH36318). IEEE

  5. Wong, SS, et al. (1984) "Elevated source/drain MOSFET." 1984 International Electron Devices Meeting. IEEE

  6. Pfister JR et al (1990) A self-aligned elevated source/drain MOSFET. IEEE Electron Device Letters 11(9):365–367

    Article  Google Scholar 

  7. Jeamsaksiri W et al (2003) Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors. IEEE Transactions on Electron Devices 50(3):610–617

    Article  Google Scholar 

  8. Zhang Z, Zhang S, Chan M (2004) Self-align recessed source drain ultrathin body SOI MOSFET. IEEE Electron Device Letters 25(11):740–742

    Article  CAS  Google Scholar 

  9. Ahn C-G et al (2005) 30-nm recessed S/D SOI MOSFET with an ultrathin body and a low SDE resistance. IEEE electron device letters 26(7):486–488

    Article  CAS  Google Scholar 

  10. Ke W et al (2007) Recessed source/drain for sub-50 nm UTB SOI MOSFET. Semiconductor science and technology 22(5):577

    Article  CAS  Google Scholar 

  11. Sviličić B, Jovanović V, Suligoj T (2009) Analytical models of front-and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs. Solid State Electron 53(5):540–547

    Article  CAS  Google Scholar 

  12. Sviličić B, Jovanović V, Suligoj T (2010) Analysis of subthreshold conduction in short-channel recessed source/drain UTB SOI MOSFETs. Solid State Electron 54(5):545–551

    Article  CAS  Google Scholar 

  13. Saramekala GK et al (2013) An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (re-S/D) SOI MOSFET. Superlattice Microst 60:580–595

    Article  CAS  Google Scholar 

  14. Kumar A, Tiwari PK (2014) A threshold voltage model of short-channel fully-depleted recessed-source/drain (re-S/D) UTB SOI MOSFETs including substrate induced surface potential effects. Solid State Electron 95:52–60

    Article  CAS  Google Scholar 

  15. Saramekala GK, Tiwari PK (2016) An analytical threshold voltage model of fully depleted (FD) recessed-source/drain (re-S/D) SOI MOSFETs with Back-gate control. J Electron Mater 45(10):5367–5374

    Article  Google Scholar 

  16. Lee C-W et al (2009) Junctionless multigate field-effect transistor. Applied Physics Letters 94.5:053511

    Article  CAS  Google Scholar 

  17. Colinge J-P et al (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225

    Article  CAS  PubMed  Google Scholar 

  18. Lee C-W et al (2010) Performance estimation of junctionless multigate transistors. Solid State Electron 54(2):97–103

    Article  CAS  Google Scholar 

  19. Colinge J-P et al (2011) Junctionless nanowire transistor (JNT): properties and design guidelines. Solid State Electron 65:33–37

    Article  CAS  Google Scholar 

  20. Gnani E et al (2011) Theory of the junctionless nanowire FET. IEEE Transactions on Electron Devices 58(9):2903–2910

    Article  Google Scholar 

  21. Leung G, Chui CO (2012) Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs. IEEE Electron Device Letters 33(6):767–769

    Article  Google Scholar 

  22. Nawaz SM et al (2014) Comparison of random dopant and gate-metal workfunction variability between junctionless and conventional FinFETs. IEEE Electron Device Letters 35(6):663–665

    Article  Google Scholar 

  23. Hueting RJE et al (2008) The charge plasma PN diode. IEEE electron device letters 29(12):1367–1369

    Article  Google Scholar 

  24. Rajasekharan B et al (2010) Fabrication and characterization of the charge-plasma diode. IEEE electron device letters 31(6):528–530

    Article  CAS  Google Scholar 

  25. Kumar MJ, Nadda K (2012) Bipolar charge-plasma transistor: a novel three terminal device. IEEE Transactions on Electron Devices 59(4):962–967

    Article  CAS  Google Scholar 

  26. Kumar MJ, Janardhanan S (2013) Doping-less tunnel field effect transistor: design and investigation. IEEE transactions on Electron Devices 60(10):3285–3290

    Article  CAS  Google Scholar 

  27. Sahu C, Singh J (2014) Charge-plasma based process variation immune junctionless transistor. IEEE Electron Device Letters 35(3):411–413

    Article  CAS  Google Scholar 

  28. Gautam R et al (2012) Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: analog performance and linearity analysis. Microelectron Reliab 52(6):989–994

    Article  CAS  Google Scholar 

  29. Ghosh P et al (2012) An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. IEEE Transactions on Electron Devices 59(12):3263–3268

    Article  Google Scholar 

  30. Chaujar R et al (2008) Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design. Superlattices and Microstructures 44.2:143–152

    Article  CAS  Google Scholar 

  31. Kang S, Choi B, Kim B (2003) Linearity analysis of CMOS for RF application. IEEE transactions on microwave theory and techniques 51(3):972–977

    Article  Google Scholar 

  32. Ma W, Kaya S (2004) Impact of device physics on DG and SOI MOSFET linearity. Solid State Electron 48(10–11):1741–1746

    Article  CAS  Google Scholar 

  33. Kaya S, Ma W (2004) Optimization of RF linearity in DG-MOSFETs. IEEE Electron Device Letters 25(5):308–310

    Article  CAS  Google Scholar 

  34. Song Y et al (2014) III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications. IEEE Electron Device Letters 35(3):324–326

    Article  CAS  Google Scholar 

  35. Verma, PK, Rawat, AS, and Gupta, SK (2020) "Temperature-Dependent Analog, RF, and Linearity Analysis of Junctionless Quadruple Gate MOSFETs for Analog Applications." Advances in VLSI, Communication, and Signal Processing. Springer, Singapore, 355–366

  36. Verma, PK, et al (2020) "A Novel Dual Material Extra Insulator Layer Fin Field Effect Transistor for High-Performance Nanoscale Applications." Advances in VLSI, Communication, and Signal Processing. Springer, Singapore, 377–385

  37. Gupta SK, Baishya S (2015) Analog and RF Performance Analysis of a Junctionless Electrically Induced Source/Drain Extension Cylindrical Surround Gate (JLEJ-CSG) MOSFET. Journal of The Institution of Engineers (India): Series B 96.3:211–216

    Article  Google Scholar 

  38. Gupta SK, Baishya S (2014) On the analog and radio frequency performance of Junctionless single metal gate cylindrical surround gate metal-oxide–semiconductor field-effect transistors. Simulation 90(10):1119–1128

    Article  Google Scholar 

  39. Sahay S, and Kumar MJ (2019) Junctionless field-effect transistors: design, modeling, and simulation. John Wiley & Sons

  40. Manual, Atlas User’S. "Santa Clara, CA: Silvaco." (2017)

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Acknowledgments

The authors would like to express heartfelt thanks to the VLSI laboratory of MNNIT Allahabad, for providing resources to use SILVACO TCAD for numerical investigations of the device structures.

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  1. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, Prayagraj, Uttar Pradesh, 211004, India

    Prateek Kishor Verma & Santosh Kumar Gupta

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  1. Prateek Kishor Verma
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  2. Santosh Kumar Gupta
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Correspondence to Prateek Kishor Verma.

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Verma, P.K., Gupta, S.K. Proposal of Charge Plasma Based Recessed Source/Drain Dopingless Junctionless Transistor and its Linearity Distortion Analysis for Circuit Applications. Silicon 13, 37–64 (2021). https://doi.org/10.1007/s12633-020-00402-8

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  • DOI: https://doi.org/10.1007/s12633-020-00402-8

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