Abstract
In this work, the impact of SiO2 dielectric channel modulation along with metalloid T-shaped source-drain on the analog-RF characteristics of gate-all-around Junctionless Nanowire Transistor (JNT) has been analysed. Metalloid T-shaped source-drain contacts create the charge plasma therefore it is also referred as Charge Plasma Transistor (CPT). Impact of different source/drain materials on band gap energy, drain current, transconductance etc. is studied. Ambipolarity, Non-linear behavior and impact of high temperature on novel CPT-JNT device have also been analysed. A dielectric modulated CPT-JNT is proposed. Results demonstrate that charge plasma technique resolve the degeneracy problem of semiconductor in junctionless transistor. Use of dielectric pocket completely reduces the ambipolar nature of CPT-JNT. Use of Charge plasma technique along with gate-all-around junctionless transistor tremendously increases transconductance, device gain (current and power). The device is well suitable for analog/RF applications.
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T. Wang, L. Lou, C. Lee, A junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications. IEEE Electron Devices Lett. 34(4), 478–480 (2013)
J.-P. Colinge, C.W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. Kelleher, B. McCarthy, R. Murphy, Nanowire transistors without junctions. Nat. Nanotechnol. 5(3), 225–229 (2010)
C. Li, Y. Zhuang, S. Di, R. Han, Subthreshold behavior models for nanoscale short-channel junctionless cylindrical surrounding-gate MOSFETs. IEEE Trans. Electron Devices 60(11), 3655–3662 (2013)
G. Hu, P. Xiang, Z. Ding, R. Liu, L. Wang, T.-A. Tang, Analytical models for electric potential, threshold voltage, and subthreshold swing of junctionless surrounding gate transistor. IEEE Trans. Electron Devices 61(3), 688–695 (2014)
Y. Pratap, S. Haldar, R.S. Gupta, M. Gupta, Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design. IEEE Trans. Device Mater. Reliab. 14(1), 418–425 (2014)
N.D. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice (Springer, Berlin, 1993)
R. Kim, U.E. Avci, I.A. Young, Source/drain doping effects and performance analysis of ballistic III-V n-MOSFETs. IEEE Electron Devices Soc. 03(1), 37–43 (2015)
C. Sin, X. Sun, T.-J.K. Liu, Study of random-dopant-fluctuation (RDF) effects for the trigate bulk MOSFET. IEEE Trans. Electron Devices 56(7), 1538–1542 (2009)
C. Shin, J.-K. Kim, G.-S. Kim, H. Lee, C. Shin, J.-K. Kim, B.J. Cho, H.-Y. Yu, Random dopant fluctuation-induced threshold voltage variation-immune Ge FinFET with metal–interlayer–semiconductor source/drain. IEEE Trans. Electron Devices 63(11), 4167–4172 (2016)
Y. Pratap, P. Ghosh, S. Haldar, R.S. Gupta, M. Gupta, An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering. Microelectron. J. 85(4), 408–415 (2014)
S.A. Loana, S. Kumar, A.M. Alamoud, Novel double gate metal source/drain Schottky MOSFET as an inverter. Superlattices Microstruct. 91, 78–89 (2016)
M. Kobayashia, A. Kinoshita, K. Saraswat, H.-S. Philip Wong, Y. Nishi, Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application. J. Appl. Phys. 105, 023702 (2009)
M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 60(10), 3285–3290 (2013). https://doi.org/10.1109/TED.2013.2276888
N. Trivedi, M. Kumar, S. Haldar, S.S. Deswal, M. Gupta, R.S. Gupta, Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement. Appl. Phys. A Solids Surf. 123, 564 (2017)
S. Singh, A. Raman, Gate-all-around charge plasma-based dual material gate-stack nanowire FET for enhanced analog performance. IEEE Trans. Electron Devices (2018). https://doi.org/10.1109/TED.2018.2816898
SILVACO Int. Santa Clara, CA, ATLAS 3D DEVICE Simulator (2020)
J.W. Slotboom, H.C. de Graaff, Measurements of bandgap narrowing in Si bipolar transistors. Solid-State Electron. 19, 857–862 (1976)
J. Dorkel, Ph Leturcq, Carrier mobilities in silicon semi-empirically related to temperature doping and injection level. Solid-State Electron. 24, 821–825 (1981)
Y. Kawaguchi, T. Suzuki, S. Kawaji, Carrier concentration dependence and temperature dependence of mobility in silicon (100) N-channel inversion layers at low temperature. Solid State Commun. 36(03), 257–259 (1980)
K.-H. Kao, A.S. Verhulst, W.G. Vandenberghe, B. Sorée, G. Groeseneken, K.D. Meyer, Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans. Electron Devices 59(2), 292–301 (2012)
A. Goel, S. Rewari, S. Verma et al., Modeling of shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET gate-induced drain leakage (GIDL). Indian J. Phys. 95, 299–308 (2021)
A. Goel, S. Rewari, S. Verma et al., Shallow extension engineered dual material surrounding gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance. AEU Int. J. Electron. Commun. 111, (2019)
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Pratap, Y., Kumar, S., Gupta, R.S. et al. Performance evaluation of dielectric modulation and metalloid T-shaped source/drain on gate-all-around junctionless transistor for improved analog/RF application. J Mater Sci: Mater Electron 32, 10943–10950 (2021). https://doi.org/10.1007/s10854-021-05754-4
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DOI: https://doi.org/10.1007/s10854-021-05754-4